| Line 512... |
Line 512... |
l.nop
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l.nop
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l.nop
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l.nop
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l.movhi r5, hi(0x44004800) /* Put "l.jr r9" instruction in r5 */
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l.movhi r5, hi(0x44004800) /* Put "l.jr r9" instruction in r5 */
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l.ori r5, r5, lo(0x44004800)
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l.ori r5, r5, lo(0x44004800)
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l.sw 0x0(r0), r5 /* Write "l.j r9" to address 0x0 in RAM */
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l.sw 0x0(r0), r5 /* Write "l.j r9" to address 0x0 in RAM */
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l.movhi r5, 0xff00 /* Put an illegal instruction in r5 */
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l.movhi r5, 0xee00 /* Put an illegal instruction in r5 */
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l.sw 0x4(r0), r5 /* Write illegal instruction to RAM addr 0x4 */
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l.sw 0x4(r0), r5 /* Write illegal instruction to RAM addr 0x4 */
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l.movhi r5, 0x1500 /* l.nop after illegal instruction */
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l.sw 0x8(r0), r5 /* Write nop to RAM addr 0x8 */
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l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
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l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
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/* Call 0x4, illegal opcode instruction */
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/* Call 0x4, illegal opcode instruction */
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l.ori r6, r0, 0x4
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l.ori r6, r0, 0x4
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l.jalr r6 /* Jump to address 0x4, landing on an illegal instruction */
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l.jalr r6 /* Jump to address 0x4, landing on an illegal instruction */
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l.addi r12,r12,1 /* Increment 2nd exception counter */
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l.addi r12,r12,1 /* Increment 2nd exception counter */
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