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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-except.S] - Diff between revs 425 and 426

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Rev 425 Rev 426
Line 517... Line 517...
        l.movhi r5, 0xee00 /* Put an illegal instruction in r5 */
        l.movhi r5, 0xee00 /* Put an illegal instruction in r5 */
        l.sw    0x4(r0), r5   /* Write illegal instruction to RAM addr 0x4 */
        l.sw    0x4(r0), r5   /* Write illegal instruction to RAM addr 0x4 */
        l.movhi r5, 0x1500 /* l.nop after illegal instruction */
        l.movhi r5, 0x1500 /* l.nop after illegal instruction */
        l.sw    0x8(r0), r5   /* Write nop to RAM addr 0x8 */
        l.sw    0x8(r0), r5   /* Write nop to RAM addr 0x8 */
        l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
        l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
        /* Call 0x4, illegal opcode instruction */
        /* Jump to 0x4 - illegal opcode instruction */
        l.ori   r6, r0, 0x4
        l.ori   r6, r0, 0x4
        l.jalr  r6 /* Jump to address 0x4, landing on an illegal instruction */
        l.jalr  r6              /* Jump to address 0x4, land on illegal insn */
        l.addi  r12,r12,1 /* Increment 2nd exception counter */
        l.addi  r12,r12,1 /* Increment 2nd exception counter */
        l.nop /* Should return here */
        l.nop /* Should return here */
        l.nop
        l.nop
 
 
        /* Test in delay slot */
        /* Test in delay slot */
 
 
        l.movhi r5, 0xff00 /* Put an illegal instruction in r5 */
        l.movhi r5, 0xee00      /* Put an illegal instruction in r5 */
        l.sw    0x4(r0), r5   /* Write illegal instruction to RAM addr 0x4 */
        l.sw    0x4(r0), r5   /* Write illegal instruction to RAM addr 0x4 */
        l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
        l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
        l.jalr  r0 /* Jump to address 0, will be a jump back but with an illegal
        l.jalr  r0 /* Jump to address 0, will be a jump back but with an illegal
                     dslot instruction which will befixed by handler */
                     dslot instruction which will befixed by handler */
        l.addi  r12,r12,1 /* Increment 2nd exception counter */
        l.addi  r12,r12,1 /* Increment 2nd exception counter */

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