| Line 82... |
Line 82... |
# error Processor has no data MMU. Cannot run this test without it.
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# error Processor has no data MMU. Cannot run this test without it.
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# error
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# error
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#endif
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#endif
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// Reduce the number of sets tested
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// Define to run only tests on SHORT_TEST_NUM TLB sets
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#define SHORT_TEST
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#define SHORT_TEST
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#define SHORT_TEST_NUM 4
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// Defines useful when wishing to skip instruction or data MMU tests when doing
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// development on one or the other.
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// Set this to 1 to enable the IMMU tests
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#define DO_IMMU_TESTS 1
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// Set this to 1 to enable the DMMU tests
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// Set this to 1 to enable the DMMU tests
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#define DO_DMMU_TESTS 1
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#define DO_DMMU_TESTS 1
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// Symbols defined in linker script
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// Symbols defined in linker script
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extern unsigned long _endtext;
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extern unsigned long _endtext;
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| Line 945... |
Line 951... |
*/
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*/
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int dtlb_dcache_test (int set)
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int dtlb_dcache_test (int set)
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{
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{
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int i, j;
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int i, j;
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unsigned long ea, ta, vmea;
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unsigned long ea, ta, vmea;
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unsigned long testwrite_to_be_cached, testwrite_not_to_be_cached;
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// This test can't be run if set==DTLB_SETS-1
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if (set==(DTLB_SETS-1))
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return 0;
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// Check data cache is present and enabled
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// Check data cache is present and enabled
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if (!(mfspr(SPR_UPR)& SPR_UPR_DCP))
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if (!(mfspr(SPR_UPR)& SPR_UPR_DCP))
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return 0;
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return 0;
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| Line 974... |
Line 985... |
ta = RAM_START + (i*PAGE_SIZE);
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ta = RAM_START + (i*PAGE_SIZE);
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mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_DTLBMR_V);
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mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_DTLBMR_V);
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mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
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mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
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}
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}
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/* Use (RAM_START + (RAM_SIZE/2)) as location we'll poke via MMUs */
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/* Configure a 1-1 mapping for it, and a high->low mapping for it */
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/* Testing page */
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/* Testing page */
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ea = RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE);
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ea = RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE);
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/* Ultimate physical address */
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ta = RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE);
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ta = RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE);
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/* Set a virtual address to translate via last TLB cache set */
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vmea = VM_BASE + RAM_START + (RAM_SIZE/2) + ((DTLB_SETS-1)*PAGE_SIZE);
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vmea = VM_BASE + RAM_START + (RAM_SIZE/2) + ((DTLB_SETS-1)*PAGE_SIZE);
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// Set a 1-1 translation for this page without cache inhibited
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// Set a 1-1 translation for this page without cache inhibited
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/* Set match register */
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/* Set match register */
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mtspr (SPR_DTLBMR_BASE(0) + set, ea | SPR_DTLBMR_V);
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mtspr (SPR_DTLBMR_BASE(0) + set, ea | SPR_DTLBMR_V);
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/* Set translate register */
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/* Set translate register */
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mtspr (SPR_DTLBTR_BASE(0) + set, ta | DTLB_PR_NOLIMIT);
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mtspr (SPR_DTLBTR_BASE(0) + set, ta | DTLB_PR_NOLIMIT);
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// Now set a far-off translation, VM_BASE, for this page with cache inhibited
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/* Now set a far-off translation, VM_BASE, for this page with cache
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// Use the last set
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using the last set */
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/* Set match register */
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/* Set match register */
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mtspr (SPR_DTLBMR_BASE(0) + (DTLB_SETS-1),
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mtspr (SPR_DTLBMR_BASE(0) + (DTLB_SETS-1), vmea | SPR_DTLBMR_V);
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vmea | SPR_DTLBMR_V);
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/* Set translate register */
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/* Set translate register */
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mtspr (SPR_DTLBTR_BASE(0) + (DTLB_SETS-1),
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mtspr (SPR_DTLBTR_BASE(0) + (DTLB_SETS-1), ta | DTLB_PR_NOLIMIT |
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ta | DTLB_PR_NOLIMIT | SPR_DTLBTR_CI);
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SPR_DTLBTR_CI);
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/* Invalidate this location in cache, to force reload when we read */
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mtspr (/*SPR_DCR_BASE(0) +*/ SPR_DCBIR, ea);
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/* Enable DMMU */
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/* Enable DMMU */
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dmmu_enable();
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dmmu_enable();
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// First do a write with the cache inhibited mapping
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// First do a write with the cache inhibited mapping
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unsigned long int testwrite_to_be_cached = 0xfeca1d0d ^ set;
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testwrite_to_be_cached = 0xfeca1d0d ^ set;
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REG32((vmea)) = testwrite_to_be_cached;
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REG32((vmea)) = testwrite_to_be_cached;
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// Read it back to check that it's the same, this read should get cached
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// Read it back to check that it's the same, this read should get cached
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ASSERT(REG32(ea) == testwrite_to_be_cached);
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ASSERT(REG32(ea) == testwrite_to_be_cached);
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// Now write again to the cache inhibited location
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// Now write again to the cache inhibited location
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unsigned long int testwrite_not_to_be_cached = 0xbaadbeef ^ set;
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testwrite_not_to_be_cached = 0xbaadbeef ^ set;
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REG32((vmea)) = testwrite_not_to_be_cached;
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REG32((vmea)) = testwrite_not_to_be_cached;
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// Now check that the cached mapping doesn't read this value back
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// Now check that the cached mapping doesn't read this value back
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ASSERT(REG32(ea) == testwrite_to_be_cached);
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ASSERT(REG32(ea) == testwrite_to_be_cached);
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// Now disable cache inhibition on the 1-1 mapping
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// Now disable cache inhibition on the 1-1 mapping
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/* Set translate register */
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/* Set translate register */
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mtspr (SPR_DTLBTR_BASE(0) + set,
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mtspr (SPR_DTLBTR_BASE(0) + set,
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ea | DTLB_PR_NOLIMIT | SPR_DTLBTR_CI);
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ea | DTLB_PR_NOLIMIT | SPR_DTLBTR_CI);
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// Check that we now get the second value we wrote
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// Check that we now get the second value we wrote
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testwrite_to_be_cached = testwrite_not_to_be_cached;
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testwrite_to_be_cached = testwrite_not_to_be_cached;
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ASSERT(REG32(ea) == testwrite_to_be_cached);
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ASSERT(REG32(ea) == testwrite_to_be_cached);
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/* Disable DMMU */
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/* Disable DMMU */
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dmmu_disable();
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dmmu_disable();
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| Line 1422... |
Line 1445... |
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int main (void)
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int main (void)
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{
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{
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int i, j;
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int i, j;
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start_text_addr = (unsigned long*)&_stext;
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start_text_addr = (unsigned long)&_stext;
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end_text_addr = (unsigned long*)&_endtext;
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end_text_addr = (unsigned long)&_endtext;
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end_data_addr = (unsigned long*)&_stack;
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end_data_addr = (unsigned long)&_stack;
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end_data_addr += 4;
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end_data_addr += 4;
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#ifndef TLB_BOTTOM_TEST_PAGE_HARDSET
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#ifndef TLB_BOTTOM_TEST_PAGE_HARDSET
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/* Set the botom MMU page (and thus TLB set) we'll begin tests at, hopefully
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avoiding pages with program text, data and stack. Determined by
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determining page after one top of stack is on. */
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TLB_TEXT_SET_NB = TLB_DATA_SET_NB = (end_data_addr+PAGE_SIZE) / PAGE_SIZE;
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TLB_TEXT_SET_NB = TLB_DATA_SET_NB = (end_data_addr+PAGE_SIZE) / PAGE_SIZE;
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#endif
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#endif
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#ifdef _UART_H_
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#ifdef _UART_H_
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uart_init(DEFAULT_UART);
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uart_init(DEFAULT_UART);
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| Line 1455... |
Line 1481... |
dtlb_translation_test ();
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dtlb_translation_test ();
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/* Virtual address match test */
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/* Virtual address match test */
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for (j = 0; j < DTLB_WAYS; j++) {
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for (j = 0; j < DTLB_WAYS; j++) {
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#ifdef SHORT_TEST
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#ifdef SHORT_TEST
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for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB+4 - 1); i++)
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for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB + SHORT_TEST_NUM - 1); i++)
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#else
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#else
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for (i = TLB_DATA_SET_NB; i < (DTLB_SETS - 1); i++)
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for (i = TLB_DATA_SET_NB; i < (DTLB_SETS - 1); i++)
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#endif
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#endif
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dtlb_match_test (j, i);
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dtlb_match_test (j, i);
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}
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}
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/* Valid bit testing */
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/* Valid bit testing */
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#ifdef SHORT_TEST
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#ifdef SHORT_TEST
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for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB+4 - 1); i++)
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for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB + SHORT_TEST_NUM - 1); i++)
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#else
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#else
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for (i = TLB_DATA_SET_NB; i < (DTLB_SETS - 1); i++)
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for (i = TLB_DATA_SET_NB; i < (DTLB_SETS - 1); i++)
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#endif
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#endif
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dtlb_valid_bit_test (i);
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dtlb_valid_bit_test (i);
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/* Permission test */
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/* Permission test */
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#ifdef SHORT_TEST
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#ifdef SHORT_TEST
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for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB+4 - 1); i++)
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for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB + SHORT_TEST_NUM - 1); i++)
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#else
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#else
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for (i = TLB_DATA_SET_NB; i < (DTLB_SETS - 1); i++)
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for (i = TLB_DATA_SET_NB; i < (DTLB_SETS - 1); i++)
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#endif
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#endif
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dtlb_permission_test (i);
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dtlb_permission_test (i);
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/* Data cache test */
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/* Data cache test */
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#ifndef OR1200_NO_DC
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#ifndef OR1200_NO_DC
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#ifdef SHORT_TEST
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#ifdef SHORT_TEST
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for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB+4 - 1); i++)
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for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB + SHORT_TEST_NUM - 1); i++)
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#else
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#else
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for (i = TLB_DATA_SET_NB; i < (DTLB_SETS - 2); i++)
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for (i = TLB_DATA_SET_NB; i < (DTLB_SETS - 2); i++)
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#endif
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#endif
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dtlb_dcache_test (i);
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dtlb_dcache_test (i);
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#endif // ifndef OR1200_NO_DC
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#endif // ifndef OR1200_NO_DC
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#endif
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#endif
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#if DO_IMMU_TESTS==1
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/* Translation test */
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/* Translation test */
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itlb_translation_test ();
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itlb_translation_test ();
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/* Virtual address match test */
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/* Virtual address match test */
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for (j = 0; j < DTLB_WAYS; j++) {
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for (j = 0; j < DTLB_WAYS; j++) {
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#ifdef SHORT_TEST
|
#ifdef SHORT_TEST
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for (i = TLB_DATA_SET_NB + 1; i < (TLB_DATA_SET_NB+4 - 1); i++)
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for (i = TLB_DATA_SET_NB + 1; i < (TLB_DATA_SET_NB + SHORT_TEST_NUM - 1); i++)
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#else
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#else
|
for (i = TLB_DATA_SET_NB + 1; i < (ITLB_SETS - 1); i++)
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for (i = TLB_DATA_SET_NB + 1; i < (ITLB_SETS - 1); i++)
|
#endif
|
#endif
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itlb_match_test (j, i);
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itlb_match_test (j, i);
|
}
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}
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/* Valid bit testing */
|
/* Valid bit testing */
|
#ifdef SHORT_TEST
|
#ifdef SHORT_TEST
|
for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB+4 - 1); i++)
|
for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB + SHORT_TEST_NUM - 1); i++)
|
#else
|
#else
|
for (i = TLB_DATA_SET_NB; i < (ITLB_SETS - 1); i++)
|
for (i = TLB_DATA_SET_NB; i < (ITLB_SETS - 1); i++)
|
#endif
|
#endif
|
itlb_valid_bit_test (i);
|
itlb_valid_bit_test (i);
|
|
|
|
|
|
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/* Permission test */
|
/* Permission test */
|
#ifdef SHORT_TEST
|
#ifdef SHORT_TEST
|
for (i = TLB_TEXT_SET_NB; i < (TLB_TEXT_SET_NB + 4); i++)
|
for (i = TLB_TEXT_SET_NB; i < (TLB_TEXT_SET_NB + SHORT_TEST_NUM); i++)
|
#else
|
#else
|
for (i = TLB_TEXT_SET_NB; i < (ITLB_SETS - 1); i++)
|
for (i = TLB_TEXT_SET_NB; i < (ITLB_SETS - 1); i++)
|
#endif
|
#endif
|
itlb_permission_test (i);
|
itlb_permission_test (i);
|
|
|
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#endif
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printf("Tests completed\n");
|
printf("Tests completed\n");
|
report (0xdeaddead);
|
report (0xdeaddead);
|
report (0x8000000d);
|
report (0x8000000d);
|
exit (0);
|
exit (0);
|
