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#include "spr-defs.h"
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#include "board.h"
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/*
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Tick timer and system call simultaneous interrupt test
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Within the test we'll use following global variables:
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r15 syscall interrupt counter
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r16 syscall function counter
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r17 timer interrupt counter
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The test do the following:
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Setup tick interrupts to occur regularly, and then do a bunch of l.sys
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systems calls, checking that they all occur OK
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Julius Baxter, julius@opencores.org
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*/
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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#define TICK_COUNTER_VALUE 8
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/* =================================================== [ exceptions ] === */
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.section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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.org 0x100
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l.movhi r0, 0
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/* Clear status register */
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l.ori r1, r0, SPR_SR_SM
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l.mtspr r0, r1, SPR_SR
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/* Clear timer */
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l.mtspr r0, r0, SPR_TTMR
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/* Init the stack */
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.global _stack
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l.movhi r1, hi(_stack)
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l.ori r1, r1, lo(_stack)
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l.addi r2, r0, -3
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l.and r1, r1, r2
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/* Jump to program initialisation code */
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.global _start
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l.movhi r4, hi(_start)
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l.ori r4, r4, lo(_start)
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l.jr r4
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l.nop
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/* =================================================== [ tick interrupt ] === */
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.org 0x500
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.global _tick_handler
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_tick_handler:
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l.addi r17, r17, 1
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# Set r7 to hold value of TTMR, one-shot mode/single run (SR)
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l.addi r5, r0, TICK_COUNTER_VALUE /* Tick timer counter value */
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l.movhi r6,hi(SPR_TTMR_SR | SPR_TTMR_IE)
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l.add r7,r5,r6
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/* Report values , 0x00000500 == tick timer report*/
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l.ori r3, r0, 0x0500
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l.nop 2
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l.or r3, r0, r17
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l.nop 2
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# Init the tick timer
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l.mtspr r0,r0,SPR_TTCR # clear TTCR
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l.mtspr r0,r7,SPR_TTMR # set TTMR
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l.rfe
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/* ========================================================= [ syscall ] === */
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.org 0xC00
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.extern _syscall_function
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.global _syscall_handler
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_syscall_handler:
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l.addi r15, r15, 1
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l.mfspr r7, r0, SPR_ESR_BASE /* Put ESR in r7, set back to ESR later */
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l.mfspr r8, r0, SPR_EPCR_BASE/* Put EPCR in r8,set back to EPCR later*/
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/* Unset IEE and TEE bits of SR */
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l.ori r4, r0, SPR_SR_IEE|SPR_SR_TEE
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l.ori r5, r0, 0xffff
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l.xor r5, r5, r4
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l.and r5, r7, r5 /* New SR without interrupt bits set */
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l.mtspr r0, r5, SPR_ESR_BASE /* SR after l.rfe */
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/* Report values , 0x00000c00 == tick timer report*/
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l.ori r3, r0, 0x0c00
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l.nop 2
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/* Get syscall number */
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l.lwz r3, -4(r8) /* r8 = load(EPCR-4)= PC of l.sys that caused this */
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l.andi r3, r3, 0xffff /* get 16-bit immediate syscall number */
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l.nop 2
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l.movhi r4, hi(_syscall_function)
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l.ori r4, r4, lo(_syscall_function)
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l.mtspr r0, r4, SPR_EPCR_BASE
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l.rfe
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/* =================================================== [ text section ] === */
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.section .text
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/* =================================================== [ start ] === */
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.global _start
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_start:
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/* Instruction cache enable */
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/* Check if IC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_ICP
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l.sfeq r26,r0
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l.bf .L8
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l.nop
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/* Disable IC */
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_ICE
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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If BS=0, 16;
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If BS=1, 32;
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r14 contain block size
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*/
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l.mfspr r24,r0,SPR_ICCFGR
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l.andi r26,r24,SPR_ICCFGR_CBS
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.sll r14,r30,r28
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/* Establish number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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*/
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l.andi r26,r24,SPR_ICCFGR_NCS
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.sll r16,r30,r28
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/* Invalidate IC */
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l.addi r6,r0,0
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l.sll r5,r14,r28
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.L7:
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l.mtspr r0,r6,SPR_ICBIR
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l.sfne r6,r5
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l.bf .L7
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l.add r6,r6,r14
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/* Enable IC */
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_ICE
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l.mtspr r0,r6,SPR_SR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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.L8:
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/* Data cache enable */
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/* Check if DC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_DCP
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l.sfeq r26,r0
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l.bf .L10
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l.nop
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/* Disable DC */
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_DCE
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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If BS=0, 16;
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If BS=1, 32;
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r14 contain block size
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*/
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l.mfspr r24,r0,SPR_DCCFGR
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l.andi r26,r24,SPR_DCCFGR_CBS
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.sll r14,r30,r28
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/* Establish number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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*/
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l.andi r26,r24,SPR_DCCFGR_NCS
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.sll r16,r30,r28
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/* Invalidate DC */
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l.addi r6,r0,0
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l.sll r5,r14,r28
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.L9:
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l.mtspr r0,r6,SPR_DCBIR
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l.sfne r6,r5
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l.bf .L9
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l.add r6,r6,r14
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/* Enable DC */
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_DCE
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l.mtspr r0,r6,SPR_SR
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.L10:
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// Kick off test
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l.jal _main
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l.nop
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/* =================================================== [ main ] === */
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.global _main
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_main:
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l.movhi r15, 0
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l.movhi r16, 0
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l.movhi r17, 0
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#
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# unmask all ints
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#
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l.movhi r5,0xffff
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l.ori r5,r5,0xffff
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l.mtspr r0,r5,SPR_PICMR # set PICMR
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# Set r20 to hold enable exceptions and interrupts
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l.mfspr r20,r0,SPR_SR
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l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE
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# Enable exceptions and interrupts
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l.mtspr r0,r20,SPR_SR # set SR
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# Set r7 to hold value of TTMR, one-shot mode/single run (SR)
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l.addi r5, r0, TICK_COUNTER_VALUE /* Tick timer counter value */
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l.movhi r6,hi(SPR_TTMR_SR | SPR_TTMR_IE)
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l.add r7,r5,r6
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# Init the tick timer
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l.mtspr r0,r0,SPR_TTCR # clear TTCR
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l.mtspr r0,r7,SPR_TTMR # set TTMR
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_wait_loop:
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l.sfeqi r17, 0x10
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l.bnf _wait_loop
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l.nop
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/* Timer is working, let's start with some syscalls */
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/* These should occur before tick timer's cycle is up */
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l.nop
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l.sys 0x1
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l.nop
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l.sys 0x2
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l.nop
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l.sys 0x3
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l.nop
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l.sys 0x4
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l.nop
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l.sys 0x5
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l.nop
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l.sfnei r16, 0xf /* Should equal 15, 0xf */
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l.bf _fail
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l.nop
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/* Continue, hopefuly now intercept tick timer cycles */
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l.nop
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l.nop
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l.sys 0x6
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l.nop
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l.nop
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l.nop
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l.nop
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l.sys 0x7
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l.nop
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l.nop
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l.sys 0x8
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l.nop
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l.nop
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l.sys 0x9
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l.nop
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l.nop
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l.sys 0xa
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l.nop
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l.nop
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l.nop
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l.sys 0xb
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l.nop
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l.nop
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l.nop
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l.nop
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l.sys 0xc
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l.nop
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l.nop
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l.sys 0xd
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l.nop
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l.nop
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l.sys 0xe
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l.nop
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l.nop
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l.sys 0xf
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l.nop
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/* Now turn off tick timer */
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l.mtspr r0,r0,SPR_TTMR # clear TTMR
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l.sfnei r16, 0x78 /* Should equal 120, 0x78 */
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l.bf _fail
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l.nop
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l.movhi r3, hi(0x8000000d)
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l.ori r3, r3, lo(0x8000000d)
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l.nop 1
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_fail:
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l.movhi r3, hi(0xbaaaaaad)
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l.ori r3, r3, lo(0xbaaaaaad)
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l.nop 1
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.global _syscall_function
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_syscall_function:
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/* r7 and r8 hold actual real ESR and EPCR, respectively */
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/* We'll restore them now */
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l.mtspr r0, r7, SPR_ESR_BASE /* SR before syscall */
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l.mtspr r0, r8, SPR_EPCR_BASE
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l.add r16, r16, r3 /* Add syscall number to our counter */
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l.movhi r4, hi(0x01000000) /* 16MB mark of memory */
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/* Ensure memory access OK */
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l.slli r3, r3, 2 /* Turn syscall number into a word address (<< 2) */
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l.add r4, r4, r3 /* Access this offset from 16MB mark */
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l.sw 0(r4), r16 /* Do a write to memory */
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l.lwz r16, 0(r4) /* Do a read from memory */
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/* Report running value of syscall counter */
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l.or r3, r0, r16
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l.nop 2
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l.rfe /* Now continue from where we had the l.sys */
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