URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [uart/] [sim/] [uart-interrupt.c] - Diff between revs 393 and 397

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Rev 393	Rev 397
Line 1...	Line 1...
`/*`	`/*`
`* UART interrupt test`	`* UART interrupt test`
`*`	`*`
`* Tests UART and interrupt routines servicing them.`	`* Tests UART and interrupt routines servicing them.`
`*`	`*`
`* Relies on testbench having uart0's tx line tied to uart1's rx line`	`* Relies on testbench having uart0's lines in loopback (rx = tx)`
`*`
`* Shows how single ISR can be used for two cores.`
`*`	`*`
`* Julius Baxter, julius.baxter@orsoc.se`	`* Julius Baxter, julius.baxter@orsoc.se`
`*`	`*`
`*/`	`*/`


`#include "uart-utils.h"`	`#include "cpu-utils.h"`
`#include "spr-defs.h"`	`#include "spr-defs.h"`
`#include "board.h"`	`#include "board.h"`
`#include "uart.h"`	`#include "uart.h"`
`#include "int.h"`	`#include "int.h"`
`#include "design-defines.h"`	`#include "orpsoc-defines.h"`

`#ifndef UART0`	`#ifndef UART0`
`# error`	`# error`
`# error UART0 missing and is required for UART interrupt (loopback) test`	`# error UART0 missing and is required for UART interrupt (loopback) test`
`# error`	`# error`
`#endif`	`#endif`
`#ifndef UART1`
`# error`
`# error UART1 missing and is required for UART interrupt (loopback) test`
`# error`
`#endif`


`struct uart_tx_ctrl`	`struct uart_tx_ctrl`
`{`	`{`
`char *bufptr;`	`char *bufptr;`
`int busy;`	`int busy;`
Line 61...	Line 53...
`char rxchar;`	`char rxchar;`
`while (uart_check_for_char(core))`	`while (uart_check_for_char(core))`
`{`	`{`
`rxchar = uart_getc(core);`	`rxchar = uart_getc(core);`
`report(0xff & rxchar);`	`report(0xff & rxchar);`
`if (rxchar == 0x2a) // when char is "*"`	`if (rxchar == 0x2a) // Exit simulation when RX char is '*'`
`exit(0x8000000d);`	`exit(0x8000000d);`
`}`	`}`
`}`	`}`
`else if ( (iir & UART_IIR_THRI) == UART_IIR_THRI)`	`else if ( (iir & UART_IIR_THRI) == UART_IIR_THRI)`
`{`	`{`
Line 111...	Line 103...

`/* Install UART core 0 interrupt handler */`	`/* Install UART core 0 interrupt handler */`
`int_add(UART0_IRQ, uart_int_handler,(void*) &uart0_core);`	`int_add(UART0_IRQ, uart_int_handler,(void*) &uart0_core);`

`/* Install UART core 1 interrupt handler */`	`/* Install UART core 1 interrupt handler */`
`int_add(UART1_IRQ, uart_int_handler,(void*) &uart1_core);`	`//int_add(UART1_IRQ, uart_int_handler,(void*) &uart1_core);`

`/* Enable interrupts in supervisor register */`	`/* Enable interrupts in supervisor register */`
`mtspr (SPR_SR, mfspr (SPR_SR) \| SPR_SR_IEE);`	`mtspr (SPR_SR, mfspr (SPR_SR) \| SPR_SR_IEE);`

`uart_init(uart0_core);`	`uart_init(uart0_core);`
`uart_init(uart1_core);`	`//uart_init(uart1_core);`

`uart_rxint_enable(uart1_core);`	`//uart_rxint_enable(uart1_core);`
	`uart_rxint_enable(uart0_core);`

`char* teststring = "\n\tHello world, and UART 1, from UART 0\n\0";`	`char* teststring = "\n\tHello world from UART 0\n\0";`

`uart0_tx_buffer(teststring);`	`uart0_tx_buffer(teststring);`

`// Do other things while we transmit`	`// Do other things while we transmit`
`float f1, f2, f3; int i;`	`float f1, f2, f3; int i;`
Line 137...	Line 130...

`char* done_calculating = "\tDone with the number crunching!\n\0";`	`char* done_calculating = "\tDone with the number crunching!\n\0";`

`uart0_tx_buffer(done_calculating);`	`uart0_tx_buffer(done_calculating);`

	`// Character '*', which will be received in the interrupt handler and cause`
	`// the simulation to exit.`
`char* finish = "*\n\0";`	`char* finish = "*\n\0";`

`uart0_tx_buffer(finish);`	`uart0_tx_buffer(finish);`

`while(1); // will exit in the rx interrupt routine`	`while(1); // will exit in the rx interrupt routine`

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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [uart/] [sim/] [uart-interrupt.c] - Diff between revs 393 and 397