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Line 47... |
//####OTHERCOPYRIGHTEND####
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//####OTHERCOPYRIGHTEND####
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//==========================================================================
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//#####DESCRIPTIONBEGIN####
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//
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//
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// Author(s): Piotr Skrzypek
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// Author(s): Piotr Skrzypek
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// Contributor: R.Diez
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// Date: 2012-06-08
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// Date: 2012-06-08
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// Purpose:
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// Purpose:
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// Description: Based on ARM code
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// Description: Based on ARM code
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//
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//
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// This code is part of RedBoot (tm).
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// This code is part of RedBoot (tm).
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| Line 169... |
Line 170... |
trampoline = CYGPKG_REDBOOT_OPENRISC_TRAMPOLINE_ADDRESS;
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trampoline = CYGPKG_REDBOOT_OPENRISC_TRAMPOLINE_ADDRESS;
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trampoline(base_addr, base_addr + length, target, entry);
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trampoline(base_addr, base_addr + length, target, entry);
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// This code is executed from the trampoline address. Trampoline never returns.
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// This code is executed from the trampoline address. Trampoline never returns.
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asm volatile (
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asm volatile (
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// All code below must be position independent,
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// as it will run on another memory address.
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// Accorting to ABI:
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// R3 is base_addr
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// R4 is base_addr + length
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// R5 is target
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// R6 is the entry point to jump to at the end
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"__tramp_start__:\n"
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"__tramp_start__:\n"
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"1: l.sfeq r3, r4\n"
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"1: l.sfeq r3, r4\n"
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" l.bf 2f\n"
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" l.bf 2f\n"
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" l.lwz r13,0x00(r3)\n"
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" l.lwz r13,0x00(r3)\n"
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" l.sw 0x00(r5), r13\n"
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" l.sw 0x00(r5), r13\n"
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" l.addi r3, r3, 4\n"
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" l.addi r3, r3, 4\n"
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#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
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" l.j 1b\n"
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" l.j 1b\n"
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" l.addi r5, r5, 4\n"
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" l.addi r5, r5, 4\n"
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#else
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" l.addi r5, r5, 4\n"
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" l.j 1b\n"
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#endif
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"2: l.jr r6\n"
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"2: l.jr r6\n"
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#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
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" l.nop\n"
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" l.nop\n"
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#endif
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"__tramp_end__:\n"
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"__tramp_end__:\n"
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: /* no output registers */
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: /* no output registers */
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: /* no input registers */
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: /* no input registers */
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: /* no clobbered registers */
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: /* no clobbered registers */
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);
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);
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