| Line 97... |
Line 97... |
|
|
.macro reset_vector name org
|
.macro reset_vector name org
|
.p2align 8
|
.p2align 8
|
.globl __exception_\name
|
.globl __exception_\name
|
__exception_\name:
|
__exception_\name:
|
|
l.movhi r0, 0
|
load32i r3,start
|
load32i r3,start
|
l.jr r3
|
l.jr r3
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop # delay slot
|
l.nop # delay slot
|
|
#endif
|
.endm
|
.endm
|
|
|
# Generic vector macro
|
# Generic vector macro
|
|
|
.macro exception_vector name org
|
.macro exception_vector name org
|
| Line 188... |
Line 191... |
# Lookup address of VSR in table and jump to it
|
# Lookup address of VSR in table and jump to it
|
# Arg 0: Pointer to HAL_SavedRegisters struct
|
# Arg 0: Pointer to HAL_SavedRegisters struct
|
# Arg 1: Vector #
|
# Arg 1: Vector #
|
load32i r5,hal_vsr_table+(\org>>6)
|
load32i r5,hal_vsr_table+(\org>>6)
|
l.lwz r5,0(r5)
|
l.lwz r5,0(r5)
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.jr r5 # To the VSR, Batman
|
l.jr r5 # To the VSR, Batman
|
|
l.or r3,r0,sp # First arg to VSR is SP
|
# First arg to VSR is SP
|
#else
|
l.or r3,r0,sp # Delay slot
|
l.or r3,r0,sp # First arg to VSR is SP
|
|
l.jr r5 # To the VSR, Batman
|
|
#endif
|
|
|
.endm
|
.endm
|
|
|
#---------------------------------------------------------------------------
|
#---------------------------------------------------------------------------
|
# Define the exception vectors.
|
# Define the exception vectors.
|
| Line 236... |
Line 242... |
load32i r4,hal_vsr_table+4 # First entry in table is unused
|
load32i r4,hal_vsr_table+4 # First entry in table is unused
|
l.ori r5,r0,CYGNUM_HAL_VSR_COUNT
|
l.ori r5,r0,CYGNUM_HAL_VSR_COUNT
|
1: l.sw 0(r4),r3
|
1: l.sw 0(r4),r3
|
l.addi r5,r5,-1
|
l.addi r5,r5,-1
|
l.sfgtsi r5,0
|
l.sfgtsi r5,0
|
|
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.bf 1b
|
l.bf 1b
|
l.addi r4,r4,4 # delay slot
|
l.addi r4,r4,4
|
|
#else
|
|
l.addi r4,r4,4
|
|
l.bf 1b
|
|
#endif
|
|
|
# Then fill in the interrupt handlers
|
# Then fill in the interrupt handlers
|
load32i r4,hal_vsr_table
|
load32i r4,hal_vsr_table
|
load32i r3,cyg_hal_default_interrupt_vsr
|
load32i r3,cyg_hal_default_interrupt_vsr
|
l.sw CYGNUM_HAL_VECTOR_INTERRUPT*4(r4),r3
|
l.sw CYGNUM_HAL_VECTOR_INTERRUPT*4(r4),r3
|
| Line 282... |
Line 294... |
l.addi r13,r0,0
|
l.addi r13,r0,0
|
l.addi r11,r0,HAL_ICACHE_SIZE
|
l.addi r11,r0,HAL_ICACHE_SIZE
|
1:
|
1:
|
l.mtspr r0,r13,SPR_ICBIR
|
l.mtspr r0,r13,SPR_ICBIR
|
l.sfne r13,r11
|
l.sfne r13,r11
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.bf 1b
|
l.bf 1b
|
l.addi r13,r13,HAL_ICACHE_LINE_SIZE
|
l.addi r13,r13,HAL_ICACHE_LINE_SIZE
|
|
#else
|
|
l.addi r13,r13,HAL_ICACHE_LINE_SIZE
|
|
l.bf 1b
|
|
#endif
|
|
|
/* Enable I-Cache */
|
/* Enable I-Cache */
|
l.mfspr r13,r0,SPR_SR
|
l.mfspr r13,r0,SPR_SR
|
l.ori r13,r13,SPR_SR_ICE
|
l.ori r13,r13,SPR_SR_ICE
|
l.mtspr r0,r13,SPR_SR
|
l.mtspr r0,r13,SPR_SR
|
| Line 307... |
Line 324... |
l.addi r10,r0,0
|
l.addi r10,r0,0
|
l.addi r11,r0,HAL_DCACHE_SIZE
|
l.addi r11,r0,HAL_DCACHE_SIZE
|
1:
|
1:
|
l.mtspr r0,r10,SPR_DCBIR
|
l.mtspr r0,r10,SPR_DCBIR
|
l.sfne r10,r11
|
l.sfne r10,r11
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.bf 1b
|
l.bf 1b
|
l.addi r10,r10,HAL_DCACHE_LINE_SIZE
|
l.addi r10,r10,HAL_DCACHE_LINE_SIZE
|
|
#else
|
|
l.addi r10,r10,HAL_DCACHE_LINE_SIZE
|
|
l.bf 1b
|
|
#endif
|
|
|
/* Enable DC */
|
/* Enable DC */
|
l.mfspr r10,r0,SPR_SR
|
l.mfspr r10,r0,SPR_SR
|
l.ori r10,r10,SPR_SR_DCE
|
l.ori r10,r10,SPR_SR_DCE
|
l.mtspr r0,r10,SPR_SR
|
l.mtspr r0,r10,SPR_SR
|
| Line 381... |
Line 403... |
1: l.sfeq r3,r5
|
1: l.sfeq r3,r5
|
l.bf 2f
|
l.bf 2f
|
l.lwz r6,0(r3)
|
l.lwz r6,0(r3)
|
l.sw 0(r4),r6
|
l.sw 0(r4),r6
|
l.addi r3,r3,4
|
l.addi r3,r3,4
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.j 1b
|
l.j 1b
|
l.addi r4,r4,4 # delay slot
|
l.addi r4,r4,4 # delay slot
|
|
#else
|
|
l.addi r4,r4,4
|
|
l.j 1b
|
|
#endif
|
2:
|
2:
|
|
|
# Copy .data section into RAM
|
# Copy .data section into RAM
|
load32i r3,__rom_data_start
|
load32i r3,__rom_data_start
|
load32i r4,__ram_data_start
|
load32i r4,__ram_data_start
|
| Line 394... |
Line 421... |
1: l.sfeq r4,r5
|
1: l.sfeq r4,r5
|
l.bf 2f
|
l.bf 2f
|
l.lwz r6,0(r3)
|
l.lwz r6,0(r3)
|
l.sw 0(r4),r6
|
l.sw 0(r4),r6
|
l.addi r3,r3,4
|
l.addi r3,r3,4
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.j 1b
|
l.j 1b
|
l.addi r4,r4,4 # delay slot
|
l.addi r4,r4,4 # delay slot
|
|
#else
|
|
l.addi r4,r4,4
|
|
l.j 1b
|
|
#endif
|
2:
|
2:
|
|
|
#endif
|
#endif
|
|
|
# clear BSS
|
# clear BSS
|
load32i r4,__bss_start
|
load32i r4,__bss_start
|
load32i r5,__bss_end
|
load32i r5,__bss_end
|
1: l.sfeq r4,r5
|
1: l.sfeq r4,r5
|
l.bf 2f
|
l.bf 2f
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop
|
l.nop
|
|
#endif
|
l.sw 0(r4),r0
|
l.sw 0(r4),r0
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.j 1b
|
l.j 1b
|
l.addi r4,r4,4
|
l.addi r4,r4,4
|
|
#else
|
|
l.addi r4,r4,4
|
|
l.j 1b
|
|
#endif
|
2:
|
2:
|
|
|
# Note: no SBSS section to clear with OpenRISC target
|
# Note: no SBSS section to clear with OpenRISC target
|
|
|
# Platform-specific initialization
|
# Platform-specific initialization
|
l.jal hal_platform_init
|
l.jal hal_platform_init
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop # delay slot
|
l.nop # delay slot
|
|
#endif
|
|
|
# call c++ constructors
|
# call c++ constructors
|
l.jal cyg_hal_invoke_constructors
|
l.jal cyg_hal_invoke_constructors
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop # delay slot
|
l.nop # delay slot
|
|
#endif
|
|
|
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
|
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
|
l.jal initialize_stub
|
l.jal initialize_stub
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop # delay slot
|
l.nop # delay slot
|
#endif
|
#endif
|
|
#endif
|
|
|
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
|
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
|
.extern hal_ctrlc_isr_init
|
.extern hal_ctrlc_isr_init
|
l.jal hal_ctrlc_isr_init
|
l.jal hal_ctrlc_isr_init
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop # delay slot
|
l.nop # delay slot
|
#endif
|
#endif
|
|
#endif
|
|
|
l.jal cyg_start # call cyg_start()
|
l.jal cyg_start # call cyg_start()
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop # delay slot
|
l.nop # delay slot
|
|
#endif
|
9:
|
9:
|
l.j 9b # if we return, loop
|
l.j 9b # if we return, loop
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop # delay slot
|
l.nop # delay slot
|
|
#endif
|
|
|
FUNC_END(start)
|
FUNC_END(start)
|
|
|
#---------------------------------------------------------------------------
|
#---------------------------------------------------------------------------
|
# This code handles the common part of all exception handlers.
|
# This code handles the common part of all exception handlers.
|
| Line 464... |
Line 515... |
|
|
# When cyg_hal_exception_handler() returns, it will jump
|
# When cyg_hal_exception_handler() returns, it will jump
|
# directly to restore_state(), which will resume execution
|
# directly to restore_state(), which will resume execution
|
# at the location of the exception.
|
# at the location of the exception.
|
l.movhi r9, hi(restore_state)
|
l.movhi r9, hi(restore_state)
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.j cyg_hal_exception_handler
|
l.j cyg_hal_exception_handler
|
l.ori r9,r9,lo(restore_state) #Delay slot
|
l.ori r9,r9,lo(restore_state) #Delay slot
|
|
#else
|
|
l.ori r9,r9,lo(restore_state)
|
|
l.j cyg_hal_exception_handler
|
|
#endif
|
|
|
# Control never reaches this point,
|
# Control never reaches this point,
|
|
|
FUNC_END(cyg_hal_default_exception_vsr)
|
FUNC_END(cyg_hal_default_exception_vsr)
|
|
|
| Line 511... |
Line 567... |
load32i r8,__interrupt_stack_base # stack base (lowest addr)
|
load32i r8,__interrupt_stack_base # stack base (lowest addr)
|
l.sfltu sp,r8 # if (sp < __interrupt_stack_base)
|
l.sfltu sp,r8 # if (sp < __interrupt_stack_base)
|
l.bf 1f # switch to interrupt stack
|
l.bf 1f # switch to interrupt stack
|
l.sfltu sp,r7 # if (sp < __interrupt_stack_top)
|
l.sfltu sp,r7 # if (sp < __interrupt_stack_top)
|
l.bf 2f # already on interrupt stack
|
l.bf 2f # already on interrupt stack
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop # delay slot
|
l.nop # delay slot
|
|
#endif
|
1: l.or sp,r7,r7 # Switch to interrupt stack
|
1: l.or sp,r7,r7 # Switch to interrupt stack
|
2: l.addi sp,sp,-8 # Make space to save old SP...
|
2: l.addi sp,sp,-8 # Make space to save old SP...
|
l.sw 0(sp),r6 # ...and save it on the stack
|
l.sw 0(sp),r6 # ...and save it on the stack
|
#endif
|
#endif
|
|
|
| Line 525... |
Line 583... |
# Log the interrupt if kernel tracing is enabled
|
# Log the interrupt if kernel tracing is enabled
|
l.ori r3,r0,0x0301 # arg1 = type = INTR,RAISE
|
l.ori r3,r0,0x0301 # arg1 = type = INTR,RAISE
|
# arg2 = vector number
|
# arg2 = vector number
|
l.ori r5,r0,r0 # arg3 = 0
|
l.ori r5,r0,r0 # arg3 = 0
|
l.jal _cyg_instrument # call instrument function
|
l.jal _cyg_instrument # call instrument function
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
|
l.nop
|
|
#endif
|
|
|
#endif
|
#endif
|
|
|
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
|
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
|
| Line 553... |
Line 614... |
l.mfspr r9,r0,SPR_PICSR
|
l.mfspr r9,r0,SPR_PICSR
|
|
|
# Any pending external interrupts ?
|
# Any pending external interrupts ?
|
l.sfnei r9,0
|
l.sfnei r9,0
|
l.bf check_for_external_interrupts
|
l.bf check_for_external_interrupts
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
|
l.nop
|
|
#endif
|
|
|
# Theoretically, the only way we could get here is if the tick timer
|
# Theoretically, the only way we could get here is if the tick timer
|
# interrupt fired, but we check to be sure that's what happened.
|
# interrupt fired, but we check to be sure that's what happened.
|
l.sfeqi r4,CYGNUM_HAL_VECTOR_TICK_TIMER
|
l.sfeqi r4,CYGNUM_HAL_VECTOR_TICK_TIMER
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.bf 3f
|
l.bf 3f
|
l.ori r3,r0,CYGNUM_HAL_INTERRUPT_RTC # delay slot
|
l.ori r3,r0,CYGNUM_HAL_INTERRUPT_RTC # delay slot
|
|
#else
|
|
l.ori r3,r0,CYGNUM_HAL_INTERRUPT_RTC
|
|
l.bf 3f
|
|
#endif
|
|
|
#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
|
#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
|
l.jal hal_spurious_IRQ
|
l.jal hal_spurious_IRQ
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop
|
l.nop
|
|
#endif
|
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
|
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
|
l.j ignore_spurious_interrupt
|
l.j ignore_spurious_interrupt
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
|
l.nop
|
|
#endif
|
|
|
# Identify the lowest numbered interrupt bit in the PIC's PSR,
|
# Identify the lowest numbered interrupt bit in the PIC's PSR,
|
# numbering the MSB as 31 and the LSB as 0
|
# numbering the MSB as 31 and the LSB as 0
|
check_for_external_interrupts:
|
check_for_external_interrupts:
|
l.ori r3,r0,0
|
l.ori r3,r0,0
|
2: l.andi r11,r9,1 # Test low bit
|
2: l.andi r11,r9,1 # Test low bit
|
l.sfnei r11,0
|
l.sfnei r11,0
|
l.bf 3f
|
l.bf 3f
|
l.srli r9,r9,1 # Shift right 1 bit
|
l.srli r9,r9,1 # Shift right 1 bit
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.j 2b
|
l.j 2b
|
l.addi r3,r3,1 # Delay slot
|
l.addi r3,r3,1 # Delay slot
|
|
#else
|
|
l.addi r3,r3,1
|
|
l.j 2b
|
|
#endif
|
3:
|
3:
|
|
|
# At this point, r3 contains the ISR number, from 0-32
|
# At this point, r3 contains the ISR number, from 0-32
|
# which will be used to index the table of ISRs
|
# which will be used to index the table of ISRs
|
l.slli r15,r3,2
|
l.slli r15,r3,2
|
| Line 592... |
Line 671... |
|
|
# Call ISR
|
# Call ISR
|
# arg0 = ISR #
|
# arg0 = ISR #
|
# arg1 = data arg associated with interrupt
|
# arg1 = data arg associated with interrupt
|
l.jalr r11
|
l.jalr r11
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop
|
l.nop
|
|
#endif
|
|
|
ignore_spurious_interrupt:
|
ignore_spurious_interrupt:
|
|
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
|
|
|
| Line 634... |
Line 715... |
# Arg 1 = object associated with interrupt
|
# Arg 1 = object associated with interrupt
|
# Arg 2 = HAL_SavedRegisters struct
|
# Arg 2 = HAL_SavedRegisters struct
|
|
|
.extern interrupt_end
|
.extern interrupt_end
|
l.jal interrupt_end # call into C to finish off
|
l.jal interrupt_end # call into C to finish off
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop
|
l.nop
|
#endif
|
#endif
|
|
#endif
|
|
|
# Fall through to restore_state...
|
# Fall through to restore_state...
|
|
|
# Return from either an interrupt or an exception
|
# Return from either an interrupt or an exception
|
#
|
#
|
| Line 710... |
Line 793... |
l.lwz r3, 3 * OR1K_GPRSIZE(sp)
|
l.lwz r3, 3 * OR1K_GPRSIZE(sp)
|
l.lwz sp, 1 * OR1K_GPRSIZE(sp)
|
l.lwz sp, 1 * OR1K_GPRSIZE(sp)
|
|
|
# All done, restore CPU state and continue
|
# All done, restore CPU state and continue
|
l.rfe
|
l.rfe
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.nop # Delay slot
|
l.nop # Delay slot
|
|
#endif
|
|
|
|
|
##-----------------------------------------------------------------------------
|
##-----------------------------------------------------------------------------
|
## Execute pending DSRs on the interrupt stack with interrupts enabled.
|
## Execute pending DSRs on the interrupt stack with interrupts enabled.
|
## Note: this can only be called from code running on a thread stack
|
## Note: this can only be called from code running on a thread stack
|
| Line 731... |
Line 816... |
l.sw 0(sp), r3 # Save entry SP
|
l.sw 0(sp), r3 # Save entry SP
|
l.mfspr r4,r0,SPR_SR
|
l.mfspr r4,r0,SPR_SR
|
l.sw 4(sp), r4 # Save interrupt state
|
l.sw 4(sp), r4 # Save interrupt state
|
l.ori r4, r4, SPR_SR_IEE|SPR_SR_TEE
|
l.ori r4, r4, SPR_SR_IEE|SPR_SR_TEE
|
l.sw 8(sp),lr
|
l.sw 8(sp),lr
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.jal cyg_interrupt_call_pending_DSRs
|
l.jal cyg_interrupt_call_pending_DSRs
|
# Enable interrupts before calling DSRs
|
l.mtspr r0, r4, SPR_SR # Enable interrupts before calling DSRs
|
l.mtspr r0, r4, SPR_SR # Delay slot
|
#else
|
|
l.mtspr r0, r4, SPR_SR # Enable interrupts before calling DSRs
|
|
l.jal cyg_interrupt_call_pending_DSRs
|
|
#endif
|
l.lwz r4, 4(sp)
|
l.lwz r4, 4(sp)
|
l.lwz lr, 8(sp)
|
l.lwz lr, 8(sp)
|
l.lwz sp, 0(sp)
|
l.lwz sp, 0(sp)
|
|
|
# Merge original interrupt state with (possibly altered) SR reg
|
# Merge original interrupt state with (possibly altered) SR reg
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l.andi r4, r4, SPR_SR_IEE|SPR_SR_TEE
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l.andi r4, r4, SPR_SR_IEE|SPR_SR_TEE
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l.mfspr r5, r0, SPR_SR
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l.mfspr r5, r0, SPR_SR
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load32i r6, ~(SPR_SR_IEE|SPR_SR_TEE)
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load32i r6, ~(SPR_SR_IEE|SPR_SR_TEE)
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l.and r5, r5, r6
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l.and r5, r5, r6
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l.or r4, r4, r5
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l.or r4, r4, r5
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|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
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l.jr r9
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l.jr r9
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l.mtspr r0, r4, SPR_SR # Delay slot
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l.mtspr r0, r4, SPR_SR # Delay slot
|
|
#else
|
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l.mtspr r0, r4, SPR_SR
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l.jr r9
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|
#endif
|
|
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FUNC_END(hal_interrupt_stack_call_pending_DSRs)
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FUNC_END(hal_interrupt_stack_call_pending_DSRs)
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#endif
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#endif
|
|
|
##-----------------------------------------------------------------------------
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##-----------------------------------------------------------------------------
|
| Line 783... |
Line 874... |
l.sw 4(sp),lr # So debugger can know caller's PC
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l.sw 4(sp),lr # So debugger can know caller's PC
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l.sw 8(sp),r5 # Save old SP on stack
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l.sw 8(sp),r5 # Save old SP on stack
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|
|
# Call function
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# Call function
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l.jalr r3
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l.jalr r3
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
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l.nop
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l.nop
|
|
#endif
|
|
|
l.lwz sp, 8(sp) # Restore original SP
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l.lwz sp, 8(sp) # Restore original SP
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l.lwz lr, 4(sp)
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l.lwz lr, 4(sp)
|
|
#ifdef CYGHWR_BRANCH_SLOT_IMPLEMENTED
|
l.jr lr # Return to caller
|
l.jr lr # Return to caller
|
l.addi sp,sp, 8 # Delay slot
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l.addi sp,sp, 8 # Delay slot
|
|
#else
|
|
l.addi sp,sp, 8
|
|
l.jr lr # Return to caller
|
|
#endif
|
|
|
FUNC_END(hal_program_new_stack)
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FUNC_END(hal_program_new_stack)
|
|
|
#---------------------------------------------------------------------------
|
#---------------------------------------------------------------------------
|
## Temporary interrupt stack
|
## Temporary interrupt stack
|
