OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [interrupts.c] - Diff between revs 621 and 799

Show entire file | Details | Blame | View Log

Rev 621 Rev 799
Line 60... Line 60...
        return 0;
        return 0;
}
}
 
 
/* Main interrupt handler */
/* Main interrupt handler */
void int_main(void) {
void int_main(void) {
        unsigned long picsr = mfspr(SPR_PICSR);   // process only the interrupts asserted at signal catch, ignore all during process
        unsigned long picsr;
        unsigned long i = 0;
        unsigned long i;
 
 
 
        // vPortDisableInterrupts();    
 
        picsr = mfspr(SPR_PICSR);   // process only the interrupts asserted at signal catch, ignore all during process
 
        i = 0;
        while(i < 32) {
        while(i < 32) {
                if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
                if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
                        (*int_handlers[i].handler)(int_handlers[i].arg);
                        (*int_handlers[i].handler)(int_handlers[i].arg);
                }
                }
                i++;
                i++;
        }
        }
 
 
        mtspr(SPR_PICSR, 0);     // clear interrupt status: all modules have level interrupts, which have to be cleared by software,
        mtspr(SPR_PICSR, 0);     // clear interrupt status: all modules have level interrupts, which have to be cleared by software,
}                               // thus this is safe, since non processed interrupts will get re-asserted soon enough
                                // thus this is safe, since non processed interrupts will get re-asserted soon enough
 
 
 
        // vPortEnableInterrupts();     
 
}
 
 
// Dummy or32 except vectors
// Dummy or32 except vectors
 
static void stall(void) {
 
        while(1);
 
}
 
 
void buserr_except(void) {
void buserr_except(void) {
 
        unsigned long epcr = mfspr(SPR_EPCR_BASE);
 
        unsigned long eear = mfspr(SPR_EEAR_BASE);
 
 
        uart_print_str("buserr_except\n\r");
        uart_print_str("buserr_except\n\r");
 
        uart_print_str("\n\r");
 
        uart_print_int(epcr);
 
        uart_print_str("\n\r");
 
        uart_print_str("\n\r");
 
        uart_print_int(eear);
 
        uart_print_str("\n\r");
 
        report(epcr);
 
        report(eear);
 
        stall();
}
}
 
 
void dpf_except(void) {
void dpf_except(void) {
        uart_print_str("dpf_except\n\r");
        uart_print_str("dpf_except\n\r");
}
}
Line 87... Line 109...
void ipf_except(void) {
void ipf_except(void) {
        uart_print_str("ipf_except\n\r");
        uart_print_str("ipf_except\n\r");
}
}
 
 
void align_except(void) {
void align_except(void) {
 
        unsigned long epcr = mfspr(SPR_EPCR_BASE);
 
        unsigned long eear = mfspr(SPR_EEAR_BASE);
 
 
        uart_print_str("align_except\n\r");
        uart_print_str("align_except\n\r");
 
        uart_print_str("\n\r");
 
        uart_print_int(epcr);
 
        uart_print_str("\n\r");
 
        uart_print_str("\n\r");
 
        uart_print_int(eear);
 
        uart_print_str("\n\r");
 
        report(epcr);
 
        report(eear);
 
        stall();
}
}
 
 
void illegal_except(void) {
void illegal_except(void) {
        uart_print_str("illegal_except\n\r");
        uart_print_str("illegal_except\n\r");
}
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.