URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [main.c] - Diff between revs 621 and 622

Rev 621	Rev 622
Line 155...	Line 155...
`}`	`}`
`}`	`}`

`static void prvSetupHardware(void) {`	`static void prvSetupHardware(void) {`
`// UART controller use 25 Mhz Wishbone bus clock, define in board.h`	`// UART controller use 25 Mhz Wishbone bus clock, define in board.h`
`uart_init();`	`uart_init(0);`

`// Initialize internal Programmable Interrupt Controller`	`// Initialize internal Programmable Interrupt Controller`
`int_init();`	`int_init();`
`}`	`}`