URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Source/] [portable/] [GCC/] [OpenRISC/] [portasm.S] - Diff between revs 621 and 624

Rev 621	Rev 624
Line 14...	Line 14...
`l.addi r4, r0, SPR_SR_IEE`	`l.addi r4, r0, SPR_SR_IEE`
`l.xori r4, r4, 0xffffffff`	`l.xori r4, r4, 0xffffffff`
`l.and r3, r3, r4 # disable External Interrupt`	`l.and r3, r3, r4 # disable External Interrupt`
`l.mtspr r0, r3, SPR_SR # update SR`	`l.mtspr r0, r3, SPR_SR # update SR`
`l.jr r9`	`l.jr r9`
	`l.nop`
`.size vPortDisableInterrupts, .-vPortDisableInterrupts`	`.size vPortDisableInterrupts, .-vPortDisableInterrupts`


`.text`	`.text`
`.global vPortEnableInterrupts`	`.global vPortEnableInterrupts`
Line 26...	Line 27...
`l.mfspr r3, r0, SPR_SR # get current SR`	`l.mfspr r3, r0, SPR_SR # get current SR`
`l.ori r3, r3, SPR_SR_TEE # enable Tick Timer Interrup`	`l.ori r3, r3, SPR_SR_TEE # enable Tick Timer Interrup`
`l.ori r3, r3, SPR_SR_IEE # enable External Interrupt`	`l.ori r3, r3, SPR_SR_IEE # enable External Interrupt`
`l.mtspr r0, r3, SPR_SR # update SR`	`l.mtspr r0, r3, SPR_SR # update SR`
`l.jr r9`	`l.jr r9`
	`l.nop`
`.size vPortEnableInterrupts, .-vPortEnableInterrupts`	`.size vPortEnableInterrupts, .-vPortEnableInterrupts`


`.macro portSAVE_REGISTER`	`.macro portSAVE_REGISTER`
`l.addi r1, r1, -116`	`l.addi r1, r1, -116`