| Line 276... |
Line 276... |
; CheckpointCompressMode = 0
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; CheckpointCompressMode = 0
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; List of dynamically loaded objects for Verilog PLI applications
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; List of dynamically loaded objects for Verilog PLI applications
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; Veriuser = veriuser.sl
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; Veriuser = veriuser.sl
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[Project]
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[Project]
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; Warning -- Do not edit the project properties directly.
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; Property names are dynamic in nature and property
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; values have special syntax. Changing property data directly
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; can result in a corrupt MPF file. All project properties
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; can be modified through project window dialogs.
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Project_Version = 6
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Project_Version = 6
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Project_DefaultLib = uart16550
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Project_DefaultLib = work
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Project_SortMethod = unused
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Project_SortMethod = unused
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Project_Files_Count = 10
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Project_Files_Count = 10
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Project_File_0 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_tfifo.v
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Project_File_0 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/raminfr.v
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Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1027977378 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1236708645 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_1 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_sync_flops.v
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Project_File_1 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_sync_flops.v
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Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1085139805 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_2 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/raminfr.v
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Project_File_2 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_tfifo.v
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Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1027977378 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_3 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_transmitter.v
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Project_File_3 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_wb.v
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Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1027977378 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_4 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_regs.v
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Project_File_4 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_debug_if.v
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Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1101115319 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_5 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_receiver.v
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Project_File_5 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_receiver.v
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Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1087569975 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_6 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_debug_if.v
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Project_File_6 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_regs.v
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Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1027977378 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_7 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_wb.v
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Project_File_7 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_transmitter.v
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Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1085142915 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_8 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_rfifo.v
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Project_File_8 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_rfifo.v
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Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1057947626 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_9 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_top.v
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Project_File_9 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_top.v
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Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1027977378 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_Sim_Count = 0
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Project_Sim_Count = 0
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Project_Folder_Count = 0
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Project_Folder_Count = 0
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Echo_Compile_Output = 0
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Echo_Compile_Output = 0
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Save_Compile_Report = 1
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Save_Compile_Report = 1
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Project_Opt_Count = 0
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Project_Opt_Count = 0
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ForceSoftPaths = 0
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ForceSoftPaths = 0
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ReOpenSourceFiles = 1
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CloseSourceFiles = 1
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ProjectStatusDelay = 5000
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ProjectStatusDelay = 5000
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VERILOG_DoubleClick = Edit
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VERILOG_DoubleClick = Edit
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VERILOG_CustomDoubleClick =
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VERILOG_CustomDoubleClick =
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SYSTEMVERILOG_DoubleClick = Edit
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SYSTEMVERILOG_DoubleClick = Edit
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SYSTEMVERILOG_CustomDoubleClick =
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SYSTEMVERILOG_CustomDoubleClick =
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| Line 335... |
Line 338... |
XML_CustomDoubleClick =
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XML_CustomDoubleClick =
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LOGFILE_DoubleClick = Edit
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LOGFILE_DoubleClick = Edit
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LOGFILE_CustomDoubleClick =
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LOGFILE_CustomDoubleClick =
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UCDB_DoubleClick = Edit
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UCDB_DoubleClick = Edit
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UCDB_CustomDoubleClick =
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UCDB_CustomDoubleClick =
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EditorState =
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Project_Major_Version = 6
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Project_Major_Version = 6
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Project_Minor_Version = 4
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Project_Minor_Version = 5
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Project_Minor_Version = 5
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Project_Minor_Version = 5
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