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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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`include "timescale.v"
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`include "soc_defines.v"
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module top(
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module top(
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//////////////////////// Clock Input ////////////////////////
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//////////////////////// Clock Input ////////////////////////
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input [1:0] clock_24, // 24 MHz
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input [1:0] clock_24, // 24 MHz
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input [1:0] clock_27, // 27 MHz
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input [1:0] clock_27, // 27 MHz
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input clock_50, // 50 MHz
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input clock_50, // 50 MHz
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endgenerate
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endgenerate
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//---------------------------------------------------
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//---------------------------------------------------
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// soc_top
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// soc_top
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`ifdef USE_DEBUG_0
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wire [255 : 0] debug_0;
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wire [255 : 0] debug_0;
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`endif
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`ifdef USE_EXT_JTAG
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wire jtag_tck_i;
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wire jtag_tms_i;
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wire jtag_tdo_i;
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wire jtag_tdi_o;
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`endif
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soc_top i_or1200_soc_top
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soc_top i_or1200_soc_top
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(
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(
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.uart_txd_0(uart_txd), // UART Transmitter
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.uart_txd_0(uart_txd), // UART Transmitter
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.uart_rxd_0(uart_rxd), // UART Receiver
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.uart_rxd_0(uart_rxd), // UART Receiver
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// .gpio_g_ext_pad_i(gpio_g_ext_pad_i),
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// .gpio_g_ext_pad_i(gpio_g_ext_pad_i),
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// .gpio_g_ext_pad_o(gpio_g_ext_pad_o),
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// .gpio_g_ext_pad_o(gpio_g_ext_pad_o),
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// .gpio_g_ext_padoe_o(gpio_g_ext_padoe_o),
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// .gpio_g_ext_padoe_o(gpio_g_ext_padoe_o),
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.boot_strap(boot_strap),
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.boot_strap(boot_strap),
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`ifdef USE_DEBUG_0
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.debug_0(debug_0),
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.debug_0(debug_0),
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`endif
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`ifdef USE_EXT_JTAG
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.jtag_tck_i(jtag_tck_i),
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.jtag_tms_i(jtag_tms_i),
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.jtag_tdo_i(jtag_tdo_i),
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.jtag_tdi_o(jtag_tdi_o),
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`endif
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.sys_clk(sysclk),
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.sys_clk(sysclk),
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.sys_rst(reset_switch)
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.sys_rst(reset_switch)
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);
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);
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//---------------------------------------------------
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//---------------------------------------------------
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// outputs
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// outputs
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// Turn on all display
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// Turn off all display
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assign hex0 = 7'h00;
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assign hex0 = 7'hff;
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assign hex1 = 7'h00;
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assign hex1 = 7'hff;
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assign hex2 = 7'h00;
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assign hex2 = 7'hff;
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assign hex3 = 7'h00;
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assign hex3 = 7'hff;
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// assign ledg = 8'hff;
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// assign ledg = 8'hff;
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assign ledr = 10'h3ff;
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assign ledr = 10'h000;
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// All inout port turn to tri-state
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// All inout port turn to tri-state
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assign dram_dq = 16'hzzzz;
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assign dram_dq = 16'hzzzz;
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assign fl_dq = 8'hzz;
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assign fl_dq = 8'hzz;
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// assign sram_dq = 16'hzzzz;
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// assign sram_dq = 16'hzzzz;
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