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https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk
[/] [or1200_soc/] [trunk/] [src/] [soc_mem_bank_2.v] - Diff between revs 2 and 21
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Rev 21 |
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input mem_stb_i,
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input mem_stb_i,
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output mem_ack_o,
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output mem_ack_o,
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output mem_err_o,
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output mem_err_o,
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output mem_rty_o,
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output mem_rty_o,
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inout [7:0] fl_dq,
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output [21:0] fl_addr,
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output fl_we_n,
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output fl_rst_n,
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output fl_oe_n,
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output fl_ce_n,
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input mem_clk_i,
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input mem_clk_i,
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input mem_rst_i
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input mem_rst_i
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);
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);
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parameter USE_NOR_FLASH = 1;
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generate
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if( USE_NOR_FLASH )
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begin
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//---------------------------------------------------
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//---------------------------------------------------
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// outputs
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// nor flash
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async_mem_if #( .AW(22), .DW(8) )
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i_flash (
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.async_dq(fl_dq),
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.async_addr(fl_addr),
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.async_ub_n(),
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.async_lb_n(),
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.async_we_n(fl_we_n),
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.async_ce_n(fl_ce_n),
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.async_oe_n(fl_oe_n),
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.wb_clk_i(mem_clk_i),
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.wb_rst_i(mem_rst_i),
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.wb_adr_i( {13'h0000, mem_addr_i[18:0]} ),
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.wb_dat_i(mem_data_i),
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.wb_we_i(mem_we_i),
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.wb_stb_i(mem_stb_i),
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.wb_cyc_i(mem_cyc_i),
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.wb_sel_i(mem_sel_i),
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.wb_dat_o(mem_data_o),
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.wb_ack_o(mem_ack_o),
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.ce_setup(4'h1),
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.op_hold(4'h3),
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.ce_hold(4'h1),
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.big_endian_if_i(1'b1),
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.lo_byte_if_i(1'b1)
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);
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//---------------------------------------------------
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// outputs for stub
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assign mem_err_o = 1'b0;
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assign mem_rty_o = 1'b0;
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assign fl_rst_n = ~mem_rst_i;
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end
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else
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begin
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//---------------------------------------------------
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// outputs for stub
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assign mem_data_o = 32'h1bad_c0de;
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assign mem_data_o = 32'h1bad_c0de;
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assign mem_ack_o = mem_cyc_i & mem_stb_i;
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assign mem_ack_o = mem_cyc_i & mem_stb_i;
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assign mem_err_o = 1'b0;
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assign mem_err_o = 1'b0;
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assign mem_rty_o = 1'b0;
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assign mem_rty_o = 1'b0;
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end
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endgenerate
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endmodule
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endmodule
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