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Line 15... |
input mem_stb_i,
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input mem_stb_i,
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output mem_ack_o,
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output mem_ack_o,
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output mem_err_o,
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output mem_err_o,
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output mem_rty_o,
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output mem_rty_o,
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inout [15:0] sram_dq,
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output [17:0] sram_addr,
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output sram_ub_n,
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output sram_lb_n,
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output sram_we_n,
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output sram_ce_n,
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output sram_oe_n,
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input mem_clk_i,
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input mem_clk_i,
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input mem_rst_i
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input mem_rst_i
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);
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);
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parameter MEM_DEPTH = 14;
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parameter USE_ON_CHIP_MEM = 0;
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parameter ON_CHIP_MEM_DEPTH = 14;
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parameter USE_ASYNC_SRAM = 1;
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generate
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if( USE_ON_CHIP_MEM )
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begin
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//---------------------------------------------------
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//---------------------------------------------------
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// ram_byte_0
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// ram_byte_0
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soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )
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soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(ON_CHIP_MEM_DEPTH), .MEM_INIT(0) )
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i_ram_byte_0 (
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i_ram_byte_0 (
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.data(mem_data_i[7:0]),
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.data(mem_data_i[7:0]),
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.addr( mem_addr_i[(MEM_DEPTH + 1):2] ),
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.addr( mem_addr_i[(ON_CHIP_MEM_DEPTH + 1):2] ),
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.we(mem_we_i & mem_sel_i[0]),
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.we(mem_we_i & mem_sel_i[0]),
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.clk(~mem_clk_i),
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.clk(~mem_clk_i),
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.q(mem_data_o[7:0])
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.q(mem_data_o[7:0])
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);
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);
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//---------------------------------------------------
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//---------------------------------------------------
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// ram_byte_1
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// ram_byte_1
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soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )
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soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(ON_CHIP_MEM_DEPTH), .MEM_INIT(0) )
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i_ram_byte_1 (
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i_ram_byte_1 (
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.data(mem_data_i[15:8]),
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.data(mem_data_i[15:8]),
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.addr( mem_addr_i[(MEM_DEPTH + 1):2] ),
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.addr( mem_addr_i[(ON_CHIP_MEM_DEPTH + 1):2] ),
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.we(mem_we_i & mem_sel_i[1]),
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.we(mem_we_i & mem_sel_i[1]),
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.clk(~mem_clk_i),
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.clk(~mem_clk_i),
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.q(mem_data_o[15:8])
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.q(mem_data_o[15:8])
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);
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);
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//---------------------------------------------------
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//---------------------------------------------------
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// ram_byte_2
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// ram_byte_2
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soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )
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soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(ON_CHIP_MEM_DEPTH), .MEM_INIT(0) )
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i_ram_byte_2 (
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i_ram_byte_2 (
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.data(mem_data_i[23:16]),
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.data(mem_data_i[23:16]),
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.addr( mem_addr_i[(MEM_DEPTH + 1):2] ),
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.addr( mem_addr_i[(ON_CHIP_MEM_DEPTH + 1):2] ),
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.we(mem_we_i & mem_sel_i[2]),
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.we(mem_we_i & mem_sel_i[2]),
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.clk(~mem_clk_i),
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.clk(~mem_clk_i),
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.q(mem_data_o[23:16])
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.q(mem_data_o[23:16])
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);
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);
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//---------------------------------------------------
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//---------------------------------------------------
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// ram_byte_3
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// ram_byte_3
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soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )
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soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(ON_CHIP_MEM_DEPTH), .MEM_INIT(0) )
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i_ram_byte_3 (
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i_ram_byte_3 (
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.data(mem_data_i[31:24]),
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.data(mem_data_i[31:24]),
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.addr( mem_addr_i[(MEM_DEPTH + 1):2] ),
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.addr( mem_addr_i[(ON_CHIP_MEM_DEPTH + 1):2] ),
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.we(mem_we_i & mem_sel_i[3]),
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.we(mem_we_i & mem_sel_i[3]),
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.clk(~mem_clk_i),
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.clk(~mem_clk_i),
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.q(mem_data_o[31:24])
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.q(mem_data_o[31:24])
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);
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);
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//---------------------------------------------------
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// outputs for on chip memory
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assign mem_ack_o = mem_cyc_i & mem_stb_i;
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assign mem_err_o = 1'b0;
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assign mem_rty_o = 1'b0;
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end
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else if( USE_ASYNC_SRAM )
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begin
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//---------------------------------------------------
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// async_mem_if
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async_mem_if #( .AW(18), .DW(16) )
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i_sram (
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.async_dq(sram_dq),
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.async_addr(sram_addr),
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.async_ub_n(sram_ub_n),
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.async_lb_n(sram_lb_n),
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.async_we_n(sram_we_n),
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.async_ce_n(sram_ce_n),
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.async_oe_n(sram_oe_n),
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.wb_clk_i(mem_clk_i),
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.wb_rst_i(mem_rst_i),
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.wb_adr_i( {13'h0000, mem_addr_i[18:0]} ),
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.wb_dat_i(mem_data_i),
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.wb_we_i(mem_we_i),
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.wb_stb_i(mem_stb_i),
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.wb_cyc_i(mem_cyc_i),
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.wb_sel_i(mem_sel_i),
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.wb_dat_o(mem_data_o),
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.wb_ack_o(mem_ack_o),
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.ce_setup(4'h0),
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.op_hold(4'h1),
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.ce_hold(4'h0),
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.big_endian_if_i(1'b1),
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.lo_byte_if_i(1'b0)
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);
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//---------------------------------------------------
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//---------------------------------------------------
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// outputs
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// outputs for async_mem_if
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assign mem_err_o = 1'b0;
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assign mem_rty_o = 1'b0;
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end
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else
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begin
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//---------------------------------------------------
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// outputs for stub
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assign mem_data_o = 32'h1bad_c0de;
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assign mem_ack_o = mem_cyc_i & mem_stb_i;
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assign mem_ack_o = mem_cyc_i & mem_stb_i;
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assign mem_err_o = 1'b0;
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assign mem_err_o = 1'b0;
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assign mem_rty_o = 1'b0;
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assign mem_rty_o = 1'b0;
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end
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endgenerate
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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