| Line 81... |
Line 81... |
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`ifdef USE_DEBUG_0
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`ifdef USE_DEBUG_0
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output [255:0] debug_0,
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output [255:0] debug_0,
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`endif
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`endif
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`ifdef USE_EXT_JTAG
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input jtag_tck_i,
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input jtag_tms_i,
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input jtag_tdo_i,
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output jtag_tdi_o,
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`endif
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input sys_clk,
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input sys_clk,
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input sys_rst
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input sys_rst
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);
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);
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| Line 94... |
Line 101... |
parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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// System
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// System
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wire cpu0_rst_o;
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wire clk_i = sys_clk;
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wire clk_i = sys_clk;
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// wire rst_i = sys_rst | cpu0_rst_o;
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wire rst_i = sys_rst;
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wire rst_i = sys_rst;
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//---------------------------------------------------
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//---------------------------------------------------
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// Instruction WISHBONE interface
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// Instruction WISHBONE interface
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wire iwb_clk_i = sys_clk;
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wire iwb_clk_i = sys_clk;
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| Line 128... |
Line 137... |
wire dwb_stb_o;
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wire dwb_stb_o;
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wire dwb_we_o;
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wire dwb_we_o;
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wire [3:0] dwb_sel_o;
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wire [3:0] dwb_sel_o;
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wire [dw-1:0] dwb_dat_o;
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wire [dw-1:0] dwb_dat_o;
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wire dwb_cab_o;
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wire dwb_cab_o;
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//---------------------------------------------------
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// External Debug Interface
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wire dbg_stall_i;
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wire [3:0] dbg_lss_o; // External Load/Store Unit Status
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wire [1:0] dbg_is_o; // External Insn Fetch Status
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wire [10:0] dbg_wp_o; // Watchpoints Outputs
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wire dbg_bp_o; // Breakpoint Output
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wire dbg_stb_i; // External Address/Data Strobe
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wire dbg_we_i; // External Write Enable
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wire [aw-1:0] dbg_adr_i; // External Address Input
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wire [dw-1:0] dbg_dat_i; // External Data Input
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wire [dw-1:0] dbg_dat_o; // External Data Output
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wire dbg_ack_o; // External Data Acknowledge (not WB compatible)
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or1200_top i_or1200_top(
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or1200_top i_or1200_top(
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//---------------------------------------------------
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//---------------------------------------------------
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// Instruction WISHBONE interface
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// Instruction WISHBONE interface
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.iwb_clk_i(iwb_clk_i), // clock input
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.iwb_clk_i(iwb_clk_i), // clock input
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| Line 176... |
Line 198... |
.dwb_bte_o(dwb_bte_o), // burst type extension
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.dwb_bte_o(dwb_bte_o), // burst type extension
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`endif
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`endif
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//---------------------------------------------------
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//---------------------------------------------------
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// External Debug Interface
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// External Debug Interface
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.dbg_stall_i(1'b0), // External Stall Input
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.dbg_stall_i(dbg_stall_i), // External Stall Input
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// .dbg_ewt_i(dbg_ewt_i), // External Watchpoint Trigger Input
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.dbg_ewt_i(1'b0), // External Watchpoint Trigger Input
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// .dbg_lss_o(dbg_lss_o), // External Load/Store Unit Status
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// .dbg_lss_o(dbg_lss_o), // External Load/Store Unit Status
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// .dbg_is_o(dbg_is_o), // External Insn Fetch Status
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// .dbg_is_o(dbg_is_o), // External Insn Fetch Status
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// .dbg_wp_o(dbg_wp_o), // Watchpoints Outputs
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// .dbg_wp_o(dbg_wp_o), // Watchpoints Outputs
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// .dbg_bp_o(dbg_bp_o), // Breakpoint Output
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.dbg_bp_o(dbg_bp_o), // Breakpoint Output
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// .dbg_stb_i(dbg_stb_i), // External Address/Data Strobe
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.dbg_stb_i(dbg_stb_i), // External Address/Data Strobe
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// .dbg_we_i(dbg_we_i), // External Write Enable
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.dbg_we_i(dbg_we_i), // External Write Enable
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// .dbg_adr_i(dbg_adr_i), // External Address Input
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.dbg_adr_i(dbg_adr_i), // External Address Input
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// .dbg_dat_i(dbg_dat_i), // External Data Input
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.dbg_dat_i(dbg_dat_i), // External Data Input
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// .dbg_dat_o(dbg_dat_o), // External Data Output
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.dbg_dat_o(dbg_dat_o), // External Data Output
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// .dbg_ack_o(dbg_ack_o), // External Data Acknowledge (not WB compatible)
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.dbg_ack_o(dbg_ack_o), // External Data Acknowledge (not WB compatible)
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//---------------------------------------------------
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//---------------------------------------------------
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// RAM BIST
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// RAM BIST
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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| Line 219... |
Line 241... |
// .pic_ints_i(pic_ints_i),
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// .pic_ints_i(pic_ints_i),
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.clk_i(clk_i),
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.clk_i(clk_i),
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.rst_i(rst_i)
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.rst_i(rst_i)
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);
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);
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//---------------------------------------------------
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// adbg_top
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wire [31:0] adbg_wb_adr_o;
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wire [31:0] adbg_wb_dat_o;
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wire [31:0] adbg_wb_dat_i;
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wire adbg_wb_cyc_o;
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wire adbg_wb_stb_o;
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wire [3:0] adbg_wb_sel_o;
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wire adbg_wb_we_o;
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wire adbg_wb_ack_i;
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wire adbg_wb_cab_o;
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wire adbg_wb_err_i;
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wire [2:0] adbg_wb_cti_o;
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wire [1:0] adbg_wb_bte_o;
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`ifdef USE_ADV_DEBUG_SYS
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soc_adv_dbg
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i_soc_adv_dbg(
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`ifdef USE_EXT_JTAG
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.jtag_tck_i(jtag_tck_i),
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.jtag_tms_i(jtag_tms_i),
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.jtag_tdo_i(jtag_tdo_i),
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.jtag_tdi_o(jtag_tdi_o),
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`endif
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.wb_clk_i(dwb_clk_i), // WISHBONE common signals
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.wb_adr_o(adbg_wb_adr_o), // WISHBONE master interface
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.wb_dat_o(adbg_wb_dat_o),
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.wb_dat_i(adbg_wb_dat_i),
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.wb_cyc_o(adbg_wb_cyc_o),
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.wb_stb_o(adbg_wb_stb_o),
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.wb_sel_o(adbg_wb_sel_o),
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.wb_we_o(adbg_wb_we_o),
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.wb_ack_i(adbg_wb_ack_i),
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.wb_cab_o(adbg_wb_cab_o),
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.wb_err_i(adbg_wb_err_i),
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.wb_cti_o(adbg_wb_cti_o),
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.wb_bte_o(adbg_wb_bte_o),
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.cpu0_clk_i(dwb_clk_i), // CPU signals
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.cpu0_addr_o(dbg_adr_i),
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.cpu0_data_i(dbg_dat_o),
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.cpu0_data_o(dbg_dat_i),
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.cpu0_bp_i(dbg_bp_o),
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.cpu0_stall_o(dbg_stall_i),
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.cpu0_stb_o(dbg_stb_i),
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.cpu0_we_o(dbg_we_i),
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.cpu0_ack_i(dbg_ack_o),
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.cpu0_rst_o(cpu0_rst_o)
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);
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`else
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assign dbg_stall_i = 1'b0;
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assign adbg_wb_dat_o = 32'h0000_0000;
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assign adbg_wb_adr_o = 32'h0000_0000;
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assign adbg_wb_sel_o = 4'h0;
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assign adbg_wb_we_o = 1'b0;
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assign adbg_wb_cyc_o = 1'b0;
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assign adbg_wb_stb_o = 1'b0;
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`endif
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//---------------------------------------------------
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//---------------------------------------------------
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// remap mux
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// remap mux
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wire [1:0] boot_remap;
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wire [1:0] boot_remap;
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// instruction wb remap mux
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// instruction wb remap mux
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| Line 359... |
Line 441... |
i_wb_conmax_top(
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i_wb_conmax_top(
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// Master 0 Interface
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// Master 0 Interface
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.m0_data_i(iwb_dat_o),
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.m0_data_i(iwb_dat_o),
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.m0_data_o(iwb_dat_i),
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.m0_data_o(iwb_dat_i),
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.m0_addr_i( iwb_remap_adr_o ),
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.m0_addr_i( iwb_remap_adr_o ),
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// .m0_addr_i( iwb_adr_o ),
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.m0_sel_i(iwb_sel_o),
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.m0_sel_i(iwb_sel_o),
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.m0_we_i(iwb_we_o),
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.m0_we_i(iwb_we_o),
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.m0_cyc_i(iwb_cyc_o),
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.m0_cyc_i(iwb_cyc_o),
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.m0_stb_i(iwb_stb_o),
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.m0_stb_i(iwb_stb_o),
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.m0_ack_o(iwb_ack_i),
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.m0_ack_o(iwb_ack_i),
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| Line 371... |
Line 452... |
.m0_rty_o(iwb_rty_i),
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.m0_rty_o(iwb_rty_i),
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// Master 1 Interface
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// Master 1 Interface
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.m1_data_i(dwb_dat_o),
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.m1_data_i(dwb_dat_o),
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.m1_data_o(dwb_dat_i),
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.m1_data_o(dwb_dat_i),
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.m1_addr_i(dwb_remap_adr_o),
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.m1_addr_i(dwb_remap_adr_o),
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// .m1_addr_i(dwb_adr_o),
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.m1_sel_i(dwb_sel_o),
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.m1_sel_i(dwb_sel_o),
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.m1_we_i(dwb_we_o),
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.m1_we_i(dwb_we_o),
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.m1_cyc_i(dwb_cyc_o),
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.m1_cyc_i(dwb_cyc_o),
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.m1_stb_i(dwb_stb_o),
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.m1_stb_i(dwb_stb_o),
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.m1_ack_o(dwb_ack_i),
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.m1_ack_o(dwb_ack_i),
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.m1_err_o(dwb_err_i),
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.m1_err_o(dwb_err_i),
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.m1_rty_o(dwb_rty_i),
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.m1_rty_o(dwb_rty_i),
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// Master 2 Interface
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// Master 2 Interface
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.m2_data_i(32'h0000_0000),
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.m2_data_i(adbg_wb_dat_o),
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.m2_addr_i(32'h0000_0000),
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.m2_data_o(adbg_wb_dat_i),
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.m2_sel_i(4'h0),
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.m2_addr_i(adbg_wb_adr_o),
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.m2_we_i(1'b0),
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.m2_sel_i(adbg_wb_sel_o),
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.m2_cyc_i(1'b0),
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.m2_we_i(adbg_wb_we_o),
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.m2_stb_i(1'b0),
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.m2_cyc_i(adbg_wb_cyc_o),
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.m2_stb_i(adbg_wb_stb_o),
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.m2_ack_o(adbg_wb_ack_i),
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.m2_err_o(adbg_wb_err_i),
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.m2_rty_o(),
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// Master 3 Interface
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// Master 3 Interface
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.m3_data_i(32'h0000_0000),
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.m3_data_i(32'h0000_0000),
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.m3_addr_i(32'h0000_0000),
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.m3_addr_i(32'h0000_0000),
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.m3_sel_i(4'h0),
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.m3_sel_i(4'h0),
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.m3_we_i(1'b0),
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.m3_we_i(1'b0),
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