| Line 12... |
Line 12... |
(
|
(
|
//////////////////////////// UART ////////////////////////////
|
//////////////////////////// UART ////////////////////////////
|
output uart_txd_0, // UART Transmitter
|
output uart_txd_0, // UART Transmitter
|
input uart_rxd_0, // UART Receiver
|
input uart_rxd_0, // UART Receiver
|
/////////////////////// SDRAM Interface ////////////////////////
|
/////////////////////// SDRAM Interface ////////////////////////
|
// inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits
|
// inout [15:0] dram_dq, // sdram data bus 16 bits
|
// output [11:0] DRAM_ADDR, // SDRAM Address bus 12 Bits
|
// output [11:0] dram_addr, // sdram address bus 12 bits
|
// output DRAM_LDQM, // SDRAM Low-byte Data Mask
|
// output dram_ldqm, // sdram low-byte data mask
|
// output DRAM_UDQM, // SDRAM High-byte Data Mask
|
// output dram_udqm, // sdram high-byte data mask
|
// output DRAM_WE_N, // SDRAM Write Enable
|
// output dram_we_n, // sdram write enable
|
// output DRAM_CAS_N, // SDRAM Column Address Strobe
|
// output dram_cas_n, // sdram column address strobe
|
// output DRAM_RAS_N, // SDRAM Row Address Strobe
|
// output dram_ras_n, // sdram row address strobe
|
// output DRAM_CS_N, // SDRAM Chip Select
|
// output dram_cs_n, // sdram chip select
|
// output DRAM_BA_0, // SDRAM Bank Address 0
|
// output dram_ba_0, // sdram bank address 0
|
// output DRAM_BA_1, // SDRAM Bank Address 0
|
// output dram_ba_1, // sdram bank address 0
|
// output DRAM_CLK, // SDRAM Clock
|
// output dram_clk, // sdram clock
|
// output DRAM_CKE, // SDRAM Clock Enable
|
// output dram_cke, // sdram clock enable
|
//////////////////////// Flash Interface ////////////////////////
|
//////////////////////// Flash Interface ////////////////////////
|
inout [7:0] fl_dq, // flash data bus 8 bits
|
inout [7:0] fl_dq, // flash data bus 8 bits
|
output [21:0] fl_addr, // flash address bus 22 bits
|
output [21:0] fl_addr, // flash address bus 22 bits
|
output fl_we_n, // flash write enable
|
output fl_we_n, // flash write enable
|
output fl_rst_n, // flash reset
|
output fl_rst_n, // flash reset
|
| Line 86... |
Line 86... |
input sys_clk,
|
input sys_clk,
|
input sys_rst
|
input sys_rst
|
);
|
);
|
|
|
|
|
// All inout port turn to tri-state
|
|
assign DRAM_DQ = 16'hzzzz;
|
|
assign FL_DQ = 8'hzz;
|
|
|
|
|
|
//---------------------------------------------------
|
//---------------------------------------------------
|
// or1200_top
|
// or1200_top
|
//---------------------------------------------------
|
//---------------------------------------------------
|
parameter dw = `OR1200_OPERAND_WIDTH;
|
parameter dw = `OR1200_OPERAND_WIDTH;
|
parameter aw = `OR1200_OPERAND_WIDTH;
|
parameter aw = `OR1200_OPERAND_WIDTH;
|
| Line 224... |
Line 219... |
// .pic_ints_i(pic_ints_i),
|
// .pic_ints_i(pic_ints_i),
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.rst_i(rst_i)
|
.rst_i(rst_i)
|
);
|
);
|
|
|
|
//---------------------------------------------------
|
|
// remap mux
|
|
wire [1:0] boot_remap;
|
|
|
|
// instruction wb remap mux
|
|
reg [1:0] iwb_remap_select;
|
|
reg [3:0] iwb_remap_nibble;
|
|
|
|
wire [31:0] iwb_remap_adr_o = { iwb_remap_nibble, iwb_adr_o[27:0] };
|
|
|
|
always @(*)
|
|
casez( { boot_remap, iwb_adr_o[31:28] } )
|
|
6'b00_????: iwb_remap_select = 2'b00;
|
|
6'b01_0000: iwb_remap_select = 2'b01;
|
|
6'b10_0000: iwb_remap_select = 2'b10;
|
|
6'b11_0000: iwb_remap_select = 2'b11;
|
|
default: iwb_remap_select = 2'b00;
|
|
endcase
|
|
|
|
always @(*)
|
|
case( iwb_remap_select )
|
|
2'b00: iwb_remap_nibble = iwb_adr_o[31:28];
|
|
2'b01: iwb_remap_nibble = 4'b0001;
|
|
2'b10: iwb_remap_nibble = 4'b0010;
|
|
2'b11: iwb_remap_nibble = 4'b0011;
|
|
endcase
|
|
|
|
// data wb remap mux
|
|
reg [1:0] dwb_remap_select;
|
|
reg [3:0] dwb_remap_nibble;
|
|
|
|
wire [31:0] dwb_remap_adr_o = { dwb_remap_nibble, dwb_adr_o[27:0] };
|
|
|
|
always @(*)
|
|
casez( { boot_remap, dwb_adr_o[31:28] } )
|
|
6'b00_????: dwb_remap_select = 2'b00;
|
|
6'b01_0000: dwb_remap_select = 2'b01;
|
|
6'b10_0000: dwb_remap_select = 2'b10;
|
|
6'b11_0000: dwb_remap_select = 2'b11;
|
|
default: dwb_remap_select = 2'b00;
|
|
endcase
|
|
|
|
always @(*)
|
|
case( dwb_remap_select )
|
|
2'b00: dwb_remap_nibble = dwb_adr_o[31:28];
|
|
2'b01: dwb_remap_nibble = 4'b0001;
|
|
2'b10: dwb_remap_nibble = 4'b0010;
|
|
2'b11: dwb_remap_nibble = 4'b0011;
|
|
endcase
|
|
|
|
|
//---------------------------------------------------
|
//---------------------------------------------------
|
// wb_conmax_top
|
// wb_conmax_top
|
|
|
// Slave 0 Interface
|
// Slave 0 Interface
|
| Line 308... |
Line 353... |
wire s6_stb_o;
|
wire s6_stb_o;
|
wire s6_ack_i;
|
wire s6_ack_i;
|
wire s6_err_i;
|
wire s6_err_i;
|
wire s6_rty_i;
|
wire s6_rty_i;
|
|
|
wire [1:0] boot_remap;
|
|
wire [aw-1:0] iwb_remap_adr;
|
|
wire [aw-1:0] dwb_remap_adr;
|
|
|
|
wb_conmax_top
|
wb_conmax_top
|
i_wb_conmax_top(
|
i_wb_conmax_top(
|
// Master 0 Interface
|
// Master 0 Interface
|
.m0_data_i(iwb_dat_o),
|
.m0_data_i(iwb_dat_o),
|
.m0_data_o(iwb_dat_i),
|
.m0_data_o(iwb_dat_i),
|
.m0_addr_i(iwb_adr_o),
|
.m0_addr_i( iwb_remap_adr_o ),
|
|
// .m0_addr_i( iwb_adr_o ),
|
.m0_sel_i(iwb_sel_o),
|
.m0_sel_i(iwb_sel_o),
|
.m0_we_i(iwb_we_o),
|
.m0_we_i(iwb_we_o),
|
.m0_cyc_i(iwb_cyc_o),
|
.m0_cyc_i(iwb_cyc_o),
|
.m0_stb_i(iwb_stb_o),
|
.m0_stb_i(iwb_stb_o),
|
.m0_ack_o(iwb_ack_i),
|
.m0_ack_o(iwb_ack_i),
|
.m0_err_o(iwb_err_i),
|
.m0_err_o(iwb_err_i),
|
.m0_rty_o(iwb_rty_i),
|
.m0_rty_o(iwb_rty_i),
|
// Master 1 Interface
|
// Master 1 Interface
|
.m1_data_i(dwb_dat_o),
|
.m1_data_i(dwb_dat_o),
|
.m1_data_o(dwb_dat_i),
|
.m1_data_o(dwb_dat_i),
|
.m1_addr_i(dwb_adr_o),
|
.m1_addr_i(dwb_remap_adr_o),
|
|
// .m1_addr_i(dwb_adr_o),
|
.m1_sel_i(dwb_sel_o),
|
.m1_sel_i(dwb_sel_o),
|
.m1_we_i(dwb_we_o),
|
.m1_we_i(dwb_we_o),
|
.m1_cyc_i(dwb_cyc_o),
|
.m1_cyc_i(dwb_cyc_o),
|
.m1_stb_i(dwb_stb_o),
|
.m1_stb_i(dwb_stb_o),
|
.m1_ack_o(dwb_ack_i),
|
.m1_ack_o(dwb_ack_i),
|
| Line 563... |
Line 606... |
.mem_stb_i(s2_stb_o),
|
.mem_stb_i(s2_stb_o),
|
.mem_ack_o(s2_ack_i),
|
.mem_ack_o(s2_ack_i),
|
.mem_err_o(s2_err_i),
|
.mem_err_o(s2_err_i),
|
.mem_rty_o(s2_rty_i),
|
.mem_rty_o(s2_rty_i),
|
|
|
|
.fl_dq(fl_dq),
|
|
.fl_addr(fl_addr),
|
|
.fl_we_n(fl_we_n),
|
|
.fl_rst_n(fl_rst_n),
|
|
.fl_oe_n(fl_oe_n),
|
|
.fl_ce_n(fl_ce_n),
|
|
|
.mem_clk_i(clk_i),
|
.mem_clk_i(clk_i),
|
.mem_rst_i(rst_i)
|
.mem_rst_i(rst_i)
|
);
|
);
|
|
|
//---------------------------------------------------
|
//---------------------------------------------------
|
| Line 582... |
Line 632... |
.mem_stb_i(s3_stb_o),
|
.mem_stb_i(s3_stb_o),
|
.mem_ack_o(s3_ack_i),
|
.mem_ack_o(s3_ack_i),
|
.mem_err_o(s3_err_i),
|
.mem_err_o(s3_err_i),
|
.mem_rty_o(s3_rty_i),
|
.mem_rty_o(s3_rty_i),
|
|
|
|
.sram_dq(sram_dq),
|
|
.sram_addr(sram_addr),
|
|
.sram_ub_n(sram_ub_n),
|
|
.sram_lb_n(sram_lb_n),
|
|
.sram_we_n(sram_we_n),
|
|
.sram_ce_n(sram_ce_n),
|
|
.sram_oe_n(sram_oe_n),
|
|
|
.mem_clk_i(clk_i),
|
.mem_clk_i(clk_i),
|
.mem_rst_i(rst_i)
|
.mem_rst_i(rst_i)
|
);
|
);
|
|
|
//---------------------------------------------------
|
//---------------------------------------------------
|
