Subversion Repositories or1200gct

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  OR1200's definitions                                        ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////  Description                                                 ////

////  Parameters of the OR1200 core                               ////

////                                                              ////

////  To Do:                                                      ////

////   - add parameters that are missing                          ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.1.1.1  2004/06/30 17:37:38  cvsadmin

// Initial import

//

//Configuration file from graphic configuration tool

`include "or1200_config.v"

//

// Operand width / register file address width

//

// (DO NOT CHANGE)

//

`define OR1200_OPERAND_WIDTH            32

`define OR1200_REGFILE_ADDR_WIDTH       5

//

// ALUOPs

//

`define OR1200_ALUOP_WIDTH      4

`define OR1200_ALUOP_NOP        4'd4

/* Order defined by arith insns that have two source operands both in regs

   (see binutils/include/opcode/or32.h) */

`define OR1200_ALUOP_ADD        4'd0

`define OR1200_ALUOP_ADDC       4'd1

`define OR1200_ALUOP_SUB        4'd2

`define OR1200_ALUOP_AND        4'd3

`define OR1200_ALUOP_OR         4'd4

`define OR1200_ALUOP_XOR        4'd5

`define OR1200_ALUOP_MUL        4'd6

`define OR1200_ALUOP_CUST5      4'd7

`define OR1200_ALUOP_SHROT      4'd8

`define OR1200_ALUOP_DIV        4'd9

`define OR1200_ALUOP_DIVU       4'd10

/* Order not specifically defined. */

`define OR1200_ALUOP_IMM        4'd11

`define OR1200_ALUOP_MOVHI      4'd12

`define OR1200_ALUOP_COMP       4'd13

`define OR1200_ALUOP_MTSR       4'd14

`define OR1200_ALUOP_MFSR       4'd15

//

// MACOPs

//

`define OR1200_MACOP_WIDTH      2

`define OR1200_MACOP_NOP        2'b00

`define OR1200_MACOP_MAC        2'b01

`define OR1200_MACOP_MSB        2'b10

//

// Shift/rotate ops

//

`define OR1200_SHROTOP_WIDTH    2

`define OR1200_SHROTOP_NOP      2'd0

`define OR1200_SHROTOP_SLL      2'd0

`define OR1200_SHROTOP_SRL      2'd1

`define OR1200_SHROTOP_SRA      2'd2

`define OR1200_SHROTOP_ROR      2'd3

// Execution cycles per instruction

`define OR1200_MULTICYCLE_WIDTH 2

`define OR1200_ONE_CYCLE                2'd0

`define OR1200_TWO_CYCLES               2'd1

// Operand MUX selects

`define OR1200_SEL_WIDTH                2

`define OR1200_SEL_RF                   2'd0

`define OR1200_SEL_IMM                  2'd1

`define OR1200_SEL_EX_FORW              2'd2

`define OR1200_SEL_WB_FORW              2'd3

//

// BRANCHOPs

//

`define OR1200_BRANCHOP_WIDTH           3

`define OR1200_BRANCHOP_NOP             3'd0

`define OR1200_BRANCHOP_J               3'd1

`define OR1200_BRANCHOP_JR              3'd2

`define OR1200_BRANCHOP_BAL             3'd3

`define OR1200_BRANCHOP_BF              3'd4

`define OR1200_BRANCHOP_BNF             3'd5

`define OR1200_BRANCHOP_RFE             3'd6

//

// LSUOPs

//

// Bit 0: sign extend

// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword

// Bit 3: 0 load, 1 store

`define OR1200_LSUOP_WIDTH              4

`define OR1200_LSUOP_NOP                4'b0000

`define OR1200_LSUOP_LBZ                4'b0010

`define OR1200_LSUOP_LBS                4'b0011

`define OR1200_LSUOP_LHZ                4'b0100

`define OR1200_LSUOP_LHS                4'b0101

`define OR1200_LSUOP_LWZ                4'b0110

`define OR1200_LSUOP_LWS                4'b0111

`define OR1200_LSUOP_LD         4'b0001

`define OR1200_LSUOP_SD         4'b1000

`define OR1200_LSUOP_SB         4'b1010

`define OR1200_LSUOP_SH         4'b1100

`define OR1200_LSUOP_SW         4'b1110

// FETCHOPs

`define OR1200_FETCHOP_WIDTH            1

`define OR1200_FETCHOP_NOP              1'b0

`define OR1200_FETCHOP_LW               1'b1

//

// Register File Write-Back OPs

//

// Bit 0: register file write enable

// Bits 2-1: write-back mux selects

`define OR1200_RFWBOP_WIDTH             3

`define OR1200_RFWBOP_NOP               3'b000

`define OR1200_RFWBOP_ALU               3'b001

`define OR1200_RFWBOP_LSU               3'b011

`define OR1200_RFWBOP_SPRS              3'b101

`define OR1200_RFWBOP_LR                3'b111

// Compare instructions

`define OR1200_COP_SFEQ       3'b000

`define OR1200_COP_SFNE       3'b001

`define OR1200_COP_SFGT       3'b010

`define OR1200_COP_SFGE       3'b011

`define OR1200_COP_SFLT       3'b100

`define OR1200_COP_SFLE       3'b101

`define OR1200_COP_X          3'b111

`define OR1200_SIGNED_COMPARE 'd3

`define OR1200_COMPOP_WIDTH     4

//

// TAGs for instruction bus

//

`define OR1200_ITAG_IDLE        4'h0    // idle bus

`define OR1200_ITAG_NI          4'h1    // normal insn

`define OR1200_ITAG_BE          4'hb    // Bus error exception

`define OR1200_ITAG_PE          4'hc    // Page fault exception

`define OR1200_ITAG_TE          4'hd    // TLB miss exception

//

// TAGs for data bus

//

`define OR1200_DTAG_IDLE        4'h0    // idle bus

`define OR1200_DTAG_ND          4'h1    // normal data

`define OR1200_DTAG_AE          4'ha    // Alignment exception

`define OR1200_DTAG_BE          4'hb    // Bus error exception

`define OR1200_DTAG_PE          4'hc    // Page fault exception

`define OR1200_DTAG_TE          4'hd    // TLB miss exception

//////////////////////////////////////////////

//

// ORBIS32 ISA specifics

//

// SHROT_OP position in machine word

`define OR1200_SHROTOP_POS              7:6

// ALU instructions multicycle field in machine word

`define OR1200_ALUMCYC_POS              9:8

//

// Instruction opcode groups (basic)

//

`define OR1200_OR32_J                 6'b000000

`define OR1200_OR32_JAL               6'b000001

`define OR1200_OR32_BNF               6'b000011

`define OR1200_OR32_BF                6'b000100

`define OR1200_OR32_NOP               6'b000101

`define OR1200_OR32_MOVHI             6'b000110

`define OR1200_OR32_XSYNC             6'b001000

`define OR1200_OR32_RFE               6'b001001

/* */

`define OR1200_OR32_JR                6'b010001

`define OR1200_OR32_JALR              6'b010010

`define OR1200_OR32_MACI              6'b010011

/* */

`define OR1200_OR32_LWZ               6'b100001

`define OR1200_OR32_LBZ               6'b100011

`define OR1200_OR32_LBS               6'b100100

`define OR1200_OR32_LHZ               6'b100101

`define OR1200_OR32_LHS               6'b100110

`define OR1200_OR32_ADDI              6'b100111

`define OR1200_OR32_ADDIC             6'b101000

`define OR1200_OR32_ANDI              6'b101001

`define OR1200_OR32_ORI               6'b101010

`define OR1200_OR32_XORI              6'b101011

`define OR1200_OR32_MULI              6'b101100

`define OR1200_OR32_MFSPR             6'b101101

`define OR1200_OR32_SH_ROTI           6'b101110

`define OR1200_OR32_SFXXI             6'b101111

/* */

`define OR1200_OR32_MTSPR             6'b110000

`define OR1200_OR32_MACMSB            6'b110001

/* */

`define OR1200_OR32_SW                6'b110101

`define OR1200_OR32_SB                6'b110110

`define OR1200_OR32_SH                6'b110111

`define OR1200_OR32_ALU               6'b111000

`define OR1200_OR32_SFXX              6'b111001

//`define OR1200_OR32_CUST5             6'b111100

/////////////////////////////////////////////////////

//

// Exceptions

//

//

// Exception vectors per OR1K architecture:

// 0xPPPPP100 - reset

// 0xPPPPP200 - bus error

// ... etc

// where P represents exception prefix.

//

// Exception vectors can be customized as per

// the following formula:

// 0xPPPPPNVV - exception N

//

// P represents exception prefix

// N represents exception N

// VV represents length of the individual vector space,

//   usually it is 8 bits wide and starts with all bits zero

//

//

// PPPPP and VV parts

//

// Sum of these two defines needs to be 28

//

`define OR1200_EXCEPT_EPH0_P 20'h00000

`define OR1200_EXCEPT_EPH1_P 20'hF0000

`define OR1200_EXCEPT_V            8'h00

//

// N part width

//

`define OR1200_EXCEPT_WIDTH 4

//

// Definition of exception vectors

//

// To avoid implementation of a certain exception,

// simply comment out corresponding line

//

`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf

`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he

`define OR1200_EXCEPT_BREAK             `OR1200_EXCEPT_WIDTH'hd

`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc

`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb

`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha

`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9

`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8

`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7

`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6

`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5

`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4

`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3

`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2

`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1

`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0

/////////////////////////////////////////////////////

//

// SPR groups

//

// Bits that define the group

`define OR1200_SPR_GROUP_BITS   15:11

// Width of the group bits

`define OR1200_SPR_GROUP_WIDTH  5

// Bits that define offset inside the group

`define OR1200_SPR_OFS_BITS 10:0

// List of groups

`define OR1200_SPR_GROUP_SYS    5'd00

`define OR1200_SPR_GROUP_DMMU   5'd01

`define OR1200_SPR_GROUP_IMMU   5'd02

`define OR1200_SPR_GROUP_DC     5'd03

`define OR1200_SPR_GROUP_IC     5'd04

`define OR1200_SPR_GROUP_MAC    5'd05

`define OR1200_SPR_GROUP_DU     5'd06

`define OR1200_SPR_GROUP_PM     5'd08

`define OR1200_SPR_GROUP_PIC    5'd09

`define OR1200_SPR_GROUP_TT     5'd10

/////////////////////////////////////////////////////

//

// System group

//

//

// System registers

//

`define OR1200_SPR_CFGR         7'd0

`define OR1200_SPR_RF           6'd32   // 1024 >> 5

`define OR1200_SPR_NPC          11'd16

`define OR1200_SPR_SR           11'd17

`define OR1200_SPR_PPC          11'd18

`define OR1200_SPR_EPCR         11'd32

`define OR1200_SPR_EEAR         11'd48

`define OR1200_SPR_ESR          11'd64

//

// SR bits

//

`define OR1200_SR_WIDTH 16

`define OR1200_SR_SM   0

`define OR1200_SR_TEE  1

`define OR1200_SR_IEE  2

`define OR1200_SR_DCE  3

`define OR1200_SR_ICE  4

`define OR1200_SR_DME  5

`define OR1200_SR_IME  6

`define OR1200_SR_LEE  7

`define OR1200_SR_CE   8

`define OR1200_SR_F    9

`define OR1200_SR_CY   10       // Unused

`define OR1200_SR_OV   11       // Unused

`define OR1200_SR_OVE  12       // Unused

`define OR1200_SR_DSX  13       // Unused

`define OR1200_SR_EPH  14

`define OR1200_SR_FO   15

`define OR1200_SR_CID  31:28    // Unimplemented

//

// Bits that define offset inside the group

//

`define OR1200_SPROFS_BITS 10:0

/////////////////////////////////////////////////////

//

// Power Management (PM)

//

// Bit positions inside PMR (don't change)

`define OR1200_PM_PMR_SDF 3:0

`define OR1200_PM_PMR_DME 4

`define OR1200_PM_PMR_SME 5

`define OR1200_PM_PMR_DCGE 6

`define OR1200_PM_PMR_UNUSED 31:7

// PMR offset inside PM group of registers

`define OR1200_PM_OFS_PMR 11'b0

// PM group

`define OR1200_SPRGRP_PM 5'd8

/////////////////////////////////////////////////////

//

// Debug Unit (DU)

//

// Number of DVR/DCR pairs if HW breakpoints enabled

`define OR1200_DU_DVRDCR_PAIRS 8

//

// Address offsets of DU registers inside DU group

//

// To not implement a register, do not define its address

//

`ifdef OR1200_DU_HWBKPTS

`define OR1200_DU_DVR0          11'd0

`define OR1200_DU_DVR1          11'd1

`define OR1200_DU_DVR2          11'd2

`define OR1200_DU_DVR3          11'd3

`define OR1200_DU_DVR4          11'd4

`define OR1200_DU_DVR5          11'd5

`define OR1200_DU_DVR6          11'd6

`define OR1200_DU_DVR7          11'd7

`define OR1200_DU_DCR0          11'd8

`define OR1200_DU_DCR1          11'd9

`define OR1200_DU_DCR2          11'd10

`define OR1200_DU_DCR3          11'd11

`define OR1200_DU_DCR4          11'd12

`define OR1200_DU_DCR5          11'd13

`define OR1200_DU_DCR6          11'd14

`define OR1200_DU_DCR7          11'd15

`endif

`define OR1200_DU_DMR1          11'd16

`ifdef OR1200_DU_HWBKPTS

`define OR1200_DU_DMR2          11'd17

`define OR1200_DU_DWCR0         11'd18

`define OR1200_DU_DWCR1         11'd19

`endif

`define OR1200_DU_DSR           11'd20

`define OR1200_DU_DRR           11'd21

`ifdef OR1200_DU_TB_IMPLEMENTED

`define OR1200_DU_TBADR         11'h0ff

`define OR1200_DU_TBIA          11'h1xx

`define OR1200_DU_TBIM          11'h2xx

`define OR1200_DU_TBAR          11'h3xx

`define OR1200_DU_TBTS          11'h4xx

`endif

// Position of offset bits inside SPR address

`define OR1200_DUOFS_BITS       10:0

// DCR bits

`define OR1200_DU_DCR_DP        0

`define OR1200_DU_DCR_CC        3:1

`define OR1200_DU_DCR_SC        4

`define OR1200_DU_DCR_CT        7:5

// DMR1 bits

`define OR1200_DU_DMR1_CW0      1:0

`define OR1200_DU_DMR1_CW1      3:2

`define OR1200_DU_DMR1_CW2      5:4

`define OR1200_DU_DMR1_CW3      7:6

`define OR1200_DU_DMR1_CW4      9:8

`define OR1200_DU_DMR1_CW5      11:10

`define OR1200_DU_DMR1_CW6      13:12

`define OR1200_DU_DMR1_CW7      15:14

`define OR1200_DU_DMR1_CW8      17:16

`define OR1200_DU_DMR1_CW9      19:18

`define OR1200_DU_DMR1_CW10     21:20

`define OR1200_DU_DMR1_ST       22

`define OR1200_DU_DMR1_BT       23

`define OR1200_DU_DMR1_DXFW     24

`define OR1200_DU_DMR1_ETE      25

// DMR2 bits

`define OR1200_DU_DMR2_WCE0     0

`define OR1200_DU_DMR2_WCE1     1

`define OR1200_DU_DMR2_AWTC     12:2

`define OR1200_DU_DMR2_WGB      23:13

// DWCR bits

`define OR1200_DU_DWCR_COUNT    15:0

`define OR1200_DU_DWCR_MATCH    31:16

// DSR bits

`define OR1200_DU_DSR_WIDTH     14

`define OR1200_DU_DSR_RSTE      0

`define OR1200_DU_DSR_BUSEE     1

`define OR1200_DU_DSR_DPFE      2

`define OR1200_DU_DSR_IPFE      3

`define OR1200_DU_DSR_TTE       4

`define OR1200_DU_DSR_AE        5

`define OR1200_DU_DSR_IIE       6

`define OR1200_DU_DSR_IE        7

`define OR1200_DU_DSR_DME       8

`define OR1200_DU_DSR_IME       9

`define OR1200_DU_DSR_RE        10

`define OR1200_DU_DSR_SCE       11

`define OR1200_DU_DSR_BE        12

`define OR1200_DU_DSR_TE        13

// DRR bits

`define OR1200_DU_DRR_RSTE      0

`define OR1200_DU_DRR_BUSEE     1

`define OR1200_DU_DRR_DPFE      2

`define OR1200_DU_DRR_IPFE      3

`define OR1200_DU_DRR_TTE       4

`define OR1200_DU_DRR_AE        5

`define OR1200_DU_DRR_IIE       6

`define OR1200_DU_DRR_IE        7

`define OR1200_DU_DRR_DME       8

`define OR1200_DU_DRR_IME       9

`define OR1200_DU_DRR_RE        10

`define OR1200_DU_DRR_SCE       11

`define OR1200_DU_DRR_BE        12

`define OR1200_DU_DRR_TE        13

/////////////////////////////////////////////////////

//

// Programmable Interrupt Controller (PIC)

//

// Address offsets of PIC registers inside PIC group

`define OR1200_PIC_OFS_PICMR 2'd0

`define OR1200_PIC_OFS_PICSR 2'd2

// Position of offset bits inside SPR address

`define OR1200_PICOFS_BITS 1:0

/////////////////////////////////////////////////////

//

// Tick Timer (TT)

//

// Address offsets of TT registers inside TT group

`define OR1200_TT_OFS_TTMR 1'd0

`define OR1200_TT_OFS_TTCR 1'd1

// Position of offset bits inside SPR group

`define OR1200_TTOFS_BITS 0

// TTMR bits

`define OR1200_TT_TTMR_TP 27:0

`define OR1200_TT_TTMR_IP 28

`define OR1200_TT_TTMR_IE 29

`define OR1200_TT_TTMR_M 31:30

//////////////////////////////////////////////

//

// MAC

//

`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0

//////////////////////////////////////////////

//

// Data MMU (DMMU)

//

//

// Address that selects between TLB TR and MR

//

`define OR1200_DTLB_TM_ADDR     7

//

// DTLBMR fields

//

`define OR1200_DTLBMR_V_BITS    0

`define OR1200_DTLBMR_CID_BITS  4:1

`define OR1200_DTLBMR_RES_BITS  11:5

`define OR1200_DTLBMR_VPN_BITS  31:13

//

// DTLBTR fields

//

`define OR1200_DTLBTR_CC_BITS   0

`define OR1200_DTLBTR_CI_BITS   1

`define OR1200_DTLBTR_WBC_BITS  2

`define OR1200_DTLBTR_WOM_BITS  3

`define OR1200_DTLBTR_A_BITS    4

`define OR1200_DTLBTR_D_BITS    5

`define OR1200_DTLBTR_URE_BITS  6

`define OR1200_DTLBTR_UWE_BITS  7

`define OR1200_DTLBTR_SRE_BITS  8

`define OR1200_DTLBTR_SWE_BITS  9

`define OR1200_DTLBTR_RES_BITS  11:10

`define OR1200_DTLBTR_PPN_BITS  31:13

//

// DTLB configuration

//

`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size

`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries

`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13

`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19

`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13

`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12

`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20

`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20

`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit

`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI

//

// Cache inhibit while DMMU is not enabled/implemented

//

// cache inhibited 0GB-4GB              1'b1

// cache inhibited 0GB-2GB              !dcpu_adr_i[31]

// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]

// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]

// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]

// cached 0GB-4GB                       1'b0

//

`define OR1200_DMMU_CI                  dcpu_adr_i[31]

//////////////////////////////////////////////

//

// Insn MMU (IMMU)

//

//

// Address that selects between TLB TR and MR

//

`define OR1200_ITLB_TM_ADDR     7

//

// ITLBMR fields

//

`define OR1200_ITLBMR_V_BITS    0

`define OR1200_ITLBMR_CID_BITS  4:1

`define OR1200_ITLBMR_RES_BITS  11:5

`define OR1200_ITLBMR_VPN_BITS  31:13

//

// ITLBTR fields

//

`define OR1200_ITLBTR_CC_BITS   0

`define OR1200_ITLBTR_CI_BITS   1

`define OR1200_ITLBTR_WBC_BITS  2

`define OR1200_ITLBTR_WOM_BITS  3

`define OR1200_ITLBTR_A_BITS    4

`define OR1200_ITLBTR_D_BITS    5

`define OR1200_ITLBTR_SXE_BITS  6

`define OR1200_ITLBTR_UXE_BITS  7

`define OR1200_ITLBTR_RES_BITS  11:8

`define OR1200_ITLBTR_PPN_BITS  31:13

//

// ITLB configuration

//

`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size

`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries

`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13

`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19

`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13

`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12

`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20

`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20

`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit

`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI

//

// Cache inhibit while IMMU is not enabled/implemented

// Note: all combinations that use icpu_adr_i cause async loop

//

// cache inhibited 0GB-4GB              1'b1

// cache inhibited 0GB-2GB              !icpu_adr_i[31]

// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]

// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]

// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]

// cached 0GB-4GB                       1'b0

//

`define OR1200_IMMU_CI                  1'b0

/////////////////////////////////////////////////

//

// Insn cache (IC)

//

//

// IC configurations

//

`ifdef OR1200_IC_1W_512B

`define OR1200_ICSIZE   9     // 512

`define OR1200_ICINDX   `OR1200_ICSIZE-2 // 7

`define OR1200_ICINDXH  `OR1200_ICSIZE-1 // 8

`define OR1200_ICTAGL   `OR1200_ICINDXH+1 // 9

`define OR1200_ICTAG    `OR1200_ICSIZE-`OR1200_ICLS // 5

`define OR1200_ICTAG_W  24

`endif

`ifdef OR1200_IC_1W_4KB

`define OR1200_ICSIZE                   12                      // 4096

`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10

`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11

`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12

`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8

`define OR1200_ICTAG_W                  21

`endif

`ifdef OR1200_IC_1W_8KB

`define OR1200_ICSIZE                   13                      // 8192

`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11

`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12

`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13

`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9

`define OR1200_ICTAG_W                  20

`endif

/////////////////////////////////////////////////

//

// Data cache (DC)

//

//

// DC configurations

//

`ifdef OR1200_DC_1W_4KB

`define OR1200_DCSIZE                   12                      // 4096

`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10

`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11

`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12

`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8

`define OR1200_DCTAG_W                  21

`endif

`ifdef OR1200_DC_1W_8KB

`define OR1200_DCSIZE                   13                      // 8192

`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11

`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12

`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13

`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9

`define OR1200_DCTAG_W                  20

`endif

//

// Base address and mask of QMEM

//

// Base address defines first address of QMEM. Mask defines

// QMEM range in address space. Actual size of QMEM is however

// determined with instantiated RAM/ROM. However bigger

// mask will reserve more address space for QMEM, but also

// make design faster, while more tight mask will take

// less address space but also make design slower. If

// instantiated RAM/ROM is smaller than space reserved with

// the mask, instatiated RAM/ROM will also be shadowed

// at higher addresses in reserved space.

//

`define OR1200_QMEM_IADDR       32'h0080_0000

`define OR1200_QMEM_IMASK       32'hfff0_0000   // Max QMEM size 1MB

`define OR1200_QMEM_DADDR  32'h0080_0000

`define OR1200_QMEM_DMASK  32'hfff0_0000 // Max QMEM size 1MB

/////////////////////////////////////////////////////

//

// VR, UPR and Configuration Registers

//

//

// VR, UPR and configuration registers are optional. If 

// implemented, operating system can automatically figure

// out how to use the processor because it knows 

// what units are available in the processor and how they

// are configured.

//

// This section must be last in or1200_defines.v file so

// that all units are already configured and thus

// configuration registers are properly set.

// 

// Offsets of VR, UPR and CFGR registers

`define OR1200_SPRGRP_SYS_VR            4'h0

`define OR1200_SPRGRP_SYS_UPR           4'h1

`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2

`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3

`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4

`define OR1200_SPRGRP_SYS_DCCFGR        4'h5

`define OR1200_SPRGRP_SYS_ICCFGR        4'h6

`define OR1200_SPRGRP_SYS_DCFGR 4'h7

// VR fields

`define OR1200_VR_REV_BITS              5:0

`define OR1200_VR_RES1_BITS             15:6

`define OR1200_VR_CFG_BITS              23:16

`define OR1200_VR_VER_BITS              31:24

// VR values

`define OR1200_VR_REV                   6'h01

`define OR1200_VR_RES1                  10'h000

`define OR1200_VR_CFG                   8'h00

`define OR1200_VR_VER                   8'h12

// UPR fields

`define OR1200_UPR_UP_BITS              0

`define OR1200_UPR_DCP_BITS             1

`define OR1200_UPR_ICP_BITS             2

`define OR1200_UPR_DMP_BITS             3

`define OR1200_UPR_IMP_BITS             4

`define OR1200_UPR_MP_BITS              5

`define OR1200_UPR_DUP_BITS             6

`define OR1200_UPR_PCUP_BITS            7

`define OR1200_UPR_PMP_BITS             8

`define OR1200_UPR_PICP_BITS            9

`define OR1200_UPR_TTP_BITS             10

`define OR1200_UPR_RES1_BITS            23:11

`define OR1200_UPR_CUP_BITS             31:24

// UPR values

`define OR1200_UPR_UP                   1'b1

`ifdef OR1200_NO_DC

`define OR1200_UPR_DCP                  1'b0

`else

`define OR1200_UPR_DCP                  1'b1

`endif

`ifdef OR1200_NO_IC

`define OR1200_UPR_ICP                  1'b0

`else

`define OR1200_UPR_ICP                  1'b1

`endif

`ifdef OR1200_NO_DMMU

`define OR1200_UPR_DMP                  1'b0

`else

`define OR1200_UPR_DMP                  1'b1

`endif

`ifdef OR1200_NO_IMMU

`define OR1200_UPR_IMP                  1'b0

`else

`define OR1200_UPR_IMP                  1'b1

`endif

`define OR1200_UPR_MP                   1'b1    // MAC always present