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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Diff between revs 617 and 788

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.3  2002/01/28 01:15:59  lampret
 
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
 
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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reg     [width-1:0]              result;
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg     [width-1:0]              shifted_rotated;
reg                             flagforw;
reg                             flagforw;
reg                             flagcomp;
reg                             flagcomp;
reg                             flag_we;
reg                             flag_we;
 
`ifdef OR1200_SIM_ALU_DIV
integer                         d1;
integer                         d1;
integer                         d2;
integer                         d2;
 
`endif
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_eq_b;
wire                            a_lt_b;
wire                            a_lt_b;
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//
//
// Central part of the ALU
// Central part of the ALU
//
//
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
        casex (alu_op)          // synopsys parallel_case full_case
        casex (alu_op)          // synopsys parallel_case
                `OR1200_ALUOP_SHROT : begin
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                                result = shifted_rotated;
                end
                end
                `OR1200_ALUOP_ADD : begin
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                                result = result_sum;
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//
//
// Generate flag and flag write enable
// Generate flag and flag write enable
//
//
always @(alu_op or result_sum or result_and or flagcomp) begin
always @(alu_op or result_sum or result_and or flagcomp) begin
        casex (alu_op)          // synopsys parallel_case full_case
        casex (alu_op)          // synopsys parallel_case
                `OR1200_ALUOP_ADD : begin
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                        flagforw = (result_sum == 32'h0000_0000);
                        flag_we = 1'b0;
                        flag_we = 1'b0;
                end
                end
                `OR1200_ALUOP_AND: begin
                `OR1200_ALUOP_AND: begin
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//
//
// First type of compare implementation
// First type of compare implementation
//
//
`ifdef OR1200_IMPL_ALU_COMP1
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case full_case
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                `OR1200_COP_SFGT:
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//
//
// Second type of compare implementation
// Second type of compare implementation
//
//
`ifdef OR1200_IMPL_ALU_COMP2
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
always @(comp_op or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case full_case
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                `OR1200_COP_SFGT:

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