| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.5 2002/08/18 19:54:47 lampret
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// Revision 1.5 2002/08/18 19:54:47 lampret
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// Added store buffer.
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// Added store buffer.
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//
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//
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// Revision 1.4 2002/02/11 04:33:17 lampret
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// Revision 1.4 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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| Line 98... |
Line 101... |
dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o, dcsb_cab_o,
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dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o, dcsb_cab_o,
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dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
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dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
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// Internal i/f
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// Internal i/f
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dc_en,
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dc_en,
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dcdmmu_adr_i, dcdmmu_cycstb_i, dcdmmu_ci_i,
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dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
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dcpu_we_i, dcpu_sel_i, dcpu_tag_i, dcpu_dat_i,
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dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
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dcpu_dat_o, dcpu_ack_o, dcpu_rty_o, dcdmmu_err_o, dcdmmu_tag_o,
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dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
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scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
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`endif
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`endif
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| Line 141... |
Line 144... |
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//
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//
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// Internal I/F
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// Internal I/F
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//
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//
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input dc_en;
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input dc_en;
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input [31:0] dcdmmu_adr_i;
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input [31:0] dcqmem_adr_i;
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input dcdmmu_cycstb_i;
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input dcqmem_cycstb_i;
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input dcdmmu_ci_i;
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input dcqmem_ci_i;
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input dcpu_we_i;
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input dcqmem_we_i;
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input [3:0] dcpu_sel_i;
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input [3:0] dcqmem_sel_i;
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input [3:0] dcpu_tag_i;
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input [3:0] dcqmem_tag_i;
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input [dw-1:0] dcpu_dat_i;
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input [dw-1:0] dcqmem_dat_i;
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output [dw-1:0] dcpu_dat_o;
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output [dw-1:0] dcqmem_dat_o;
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output dcpu_ack_o;
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output dcqmem_ack_o;
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output dcpu_rty_o;
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output dcqmem_rty_o;
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output dcdmmu_err_o;
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output dcqmem_err_o;
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output [3:0] dcdmmu_tag_o;
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output [3:0] dcqmem_tag_o;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
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//
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// RAM BIST
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// RAM BIST
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//
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//
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| Line 220... |
Line 223... |
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//
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//
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// Data to BIU is from DCRAM when DC is enabled or from LSU when
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// Data to BIU is from DCRAM when DC is enabled or from LSU when
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// DC is disabled
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// DC is disabled
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//
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//
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assign dcsb_dat_o = dcpu_dat_i;
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assign dcsb_dat_o = dcqmem_dat_i;
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//
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//
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// Bypases of the DC when DC is disabled
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// Bypases of the DC when DC is disabled
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//
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//
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assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
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assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
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assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
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assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
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assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
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assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcqmem_we_i;
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assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcdmmu_ci_i) ? 4'b1111 : dcpu_sel_i;
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assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcqmem_ci_i) ? 4'b1111 : dcqmem_sel_i;
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assign dcsb_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
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assign dcsb_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
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assign dcpu_rty_o = ~dcpu_ack_o;
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assign dcqmem_rty_o = ~dcqmem_ack_o;
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assign dcdmmu_tag_o = dcdmmu_err_o ? `OR1200_DTAG_BE : dcpu_tag_i;
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assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
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//
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//
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// DC/LSU normal and error termination
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// DC/LSU normal and error termination
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//
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//
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assign dcpu_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
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assign dcqmem_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
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assign dcdmmu_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
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assign dcqmem_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
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//
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//
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// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
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// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
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//
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//
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//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcdmmu_adr_i;
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//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcqmem_adr_i;
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//
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//
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// Select between input data generated by LSU or by BIU
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// Select between input data generated by LSU or by BIU
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//
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//
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assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcpu_dat_i;
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assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcqmem_dat_i;
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//
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//
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// Select between data generated by DCRAM or passed by BIU
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// Select between data generated by DCRAM or passed by BIU
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//
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//
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assign dcpu_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
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assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
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//
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//
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// Tag comparison
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// Tag comparison
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//
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//
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always @(tag or saved_addr or tag_v) begin
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always @(tag or saved_addr or tag_v) begin
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| Line 271... |
Line 274... |
//
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//
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or1200_dc_fsm or1200_dc_fsm(
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or1200_dc_fsm or1200_dc_fsm(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.dc_en(dc_en),
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.dc_en(dc_en),
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.dcdmmu_cycstb_i(dcdmmu_cycstb_i),
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.dcqmem_cycstb_i(dcqmem_cycstb_i),
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.dcdmmu_ci_i(dcdmmu_ci_i),
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.dcqmem_ci_i(dcqmem_ci_i),
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.dcpu_we_i(dcpu_we_i),
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.dcqmem_we_i(dcqmem_we_i),
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.dcpu_sel_i(dcpu_sel_i),
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.dcqmem_sel_i(dcqmem_sel_i),
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.tagcomp_miss(tagcomp_miss),
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.tagcomp_miss(tagcomp_miss),
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.biudata_valid(dcsb_ack_i),
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.biudata_valid(dcsb_ack_i),
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.biudata_error(dcsb_err_i),
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.biudata_error(dcsb_err_i),
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.start_addr(dcdmmu_adr_i),
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.start_addr(dcqmem_adr_i),
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.saved_addr(saved_addr),
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.saved_addr(saved_addr),
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.dcram_we(dcram_we),
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.dcram_we(dcram_we),
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.biu_read(dcfsm_biu_read),
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.biu_read(dcfsm_biu_read),
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.biu_write(dcfsm_biu_write),
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.biu_write(dcfsm_biu_write),
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.first_hit_ack(dcfsm_first_hit_ack),
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.first_hit_ack(dcfsm_first_hit_ack),
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