| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.9 2001/10/14 13:12:09 lampret
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// Revision 1.9 2001/10/14 13:12:09 lampret
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// MP3 version.
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// MP3 version.
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| Line 187... |
Line 190... |
// Bypases of the DC when DC is disabled
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// Bypases of the DC when DC is disabled
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//
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//
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assign dcbiu_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cyc_i;
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assign dcbiu_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cyc_i;
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assign dcbiu_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_stb_i;
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assign dcbiu_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_stb_i;
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assign dcbiu_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
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assign dcbiu_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
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assign dcbiu_sel_o = (dc_en & dcfsm_biu_read) ? 4'b1111 : dcpu_sel_i;
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assign dcbiu_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write) ? 4'b1111 : dcpu_sel_i;
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assign dcbiu_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
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assign dcbiu_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
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assign dcpu_rty_o = ~dcpu_ack_o;
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assign dcpu_rty_o = ~dcpu_ack_o;
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assign dcdmmu_tag_o = dcpu_tag_i;
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assign dcdmmu_tag_o = dcdmmu_err_o ? `OR1200_DTAG_BE : dcpu_tag_i;
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//
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//
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// DC/LSU normal and error termination
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// DC/LSU normal and error termination
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//
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//
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assign dcpu_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcbiu_ack_i;
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assign dcpu_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcbiu_ack_i;
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| Line 232... |
Line 235... |
.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.dc_en(dc_en),
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.dc_en(dc_en),
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.dcdmmu_cyc_i(dcdmmu_cyc_i),
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.dcdmmu_cyc_i(dcdmmu_cyc_i),
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.dcdmmu_stb_i(dcdmmu_stb_i),
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.dcdmmu_stb_i(dcdmmu_stb_i),
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// .dcdmmu_ci_i(dcdmmu_ci_i),
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.dcdmmu_ci_i(dcdmmu_ci_i),
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.dcdmmu_ci_i(1'b0),
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.dcpu_we_i(dcpu_we_i),
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.dcpu_we_i(dcpu_we_i),
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.dcpu_sel_i(dcpu_sel_i),
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.dcpu_sel_i(dcpu_sel_i),
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.tagcomp_miss(tagcomp_miss),
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.tagcomp_miss(tagcomp_miss),
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.biudata_valid(dcbiu_ack_i),
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.biudata_valid(dcbiu_ack_i),
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.biudata_error(dcbiu_err_i),
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.biudata_error(dcbiu_err_i),
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