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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.9 2001/11/30 18:59:47 simons
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// Revision 1.9 2001/11/30 18:59:47 simons
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// *** empty log message ***
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// *** empty log message ***
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Line 82... |
// Internal i/f
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// Internal i/f
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addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
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addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
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du_stall, flushpipe, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
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du_stall, flushpipe, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
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// External i/f to DC
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// External i/f to DC
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dcpu_adr_o, dcpu_cyc_o, dcpu_stb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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Line 120... |
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//
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//
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// External i/f to DC
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// External i/f to DC
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//
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//
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output [31:0] dcpu_adr_o;
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output [31:0] dcpu_adr_o;
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output dcpu_cyc_o;
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output dcpu_cycstb_o;
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output dcpu_stb_o;
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output dcpu_we_o;
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output dcpu_we_o;
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output [3:0] dcpu_sel_o;
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output [3:0] dcpu_sel_o;
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output [3:0] dcpu_tag_o;
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output [3:0] dcpu_tag_o;
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output [31:0] dcpu_dat_o;
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output [31:0] dcpu_dat_o;
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input [31:0] dcpu_dat_i;
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input [31:0] dcpu_dat_i;
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Line 139... |
reg [3:0] dcpu_sel_o;
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reg [3:0] dcpu_sel_o;
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//
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//
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// Internal I/F assignments
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// Internal I/F assignments
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//
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//
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assign lsu_stall = dcpu_rty_i & dcpu_cyc_o;
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assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;
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assign lsu_unstall = dcpu_ack_i;
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assign lsu_unstall = dcpu_ack_i;
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assign except_align = ((lsu_op == `OR1200_LSUOP_SH) | (lsu_op == `OR1200_LSUOP_LHZ) | (lsu_op == `OR1200_LSUOP_LHS)) & dcpu_adr_o[0]
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assign except_align = ((lsu_op == `OR1200_LSUOP_SH) | (lsu_op == `OR1200_LSUOP_LHZ) | (lsu_op == `OR1200_LSUOP_LHS)) & dcpu_adr_o[0]
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| ((lsu_op == `OR1200_LSUOP_SW) | (lsu_op == `OR1200_LSUOP_LWZ) | (lsu_op == `OR1200_LSUOP_LWS)) & |dcpu_adr_o[1:0];
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| ((lsu_op == `OR1200_LSUOP_SW) | (lsu_op == `OR1200_LSUOP_LWZ) | (lsu_op == `OR1200_LSUOP_LWS)) & |dcpu_adr_o[1:0];
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assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
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assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
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assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
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assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
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Line 151... |
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//
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//
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// External I/F assignments
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// External I/F assignments
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//
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//
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assign dcpu_adr_o = addrbase + addrofs;
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assign dcpu_adr_o = addrbase + addrofs;
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assign dcpu_cyc_o = du_stall | lsu_unstall ? 1'b0 : |lsu_op;
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assign dcpu_cycstb_o = du_stall | lsu_unstall ? 1'b0 : |lsu_op;
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assign dcpu_stb_o = dcpu_cyc_o;
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assign dcpu_we_o = lsu_op[3];
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assign dcpu_we_o = lsu_op[3];
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assign dcpu_tag_o = dcpu_cyc_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
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assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
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always @(lsu_op or dcpu_adr_o)
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always @(lsu_op or dcpu_adr_o)
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casex({lsu_op, dcpu_adr_o[1:0]})
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casex({lsu_op, dcpu_adr_o[1:0]})
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{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
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{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
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{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
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{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
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{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
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{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
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