URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32.v] - Diff between revs 1063 and 1077

Rev 1063	Rev 1077
Line 60...	Line 60...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2002/10/17 20:04:40 lampret`
	`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
`//`	`//`
`// Revision 1.8 2001/11/02 18:57:14 lampret`	`// Revision 1.8 2001/11/02 18:57:14 lampret`
`// Modified virtual silicon instantiations.`	`// Modified virtual silicon instantiations.`
Line 222...	Line 225...
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.scanb_rst(scanb_rst),`
`.scanb_si(scanb_si),`	`.scanb_si(scanb_si),`
`.scanb_so(scanb_so),`	`.scanb_so(scanb_so),`
`.scanb_en(scanb_en),`	`.scanb_en(scanb_en),`
`.canb_clk(scanb_clk),`	`.scanb_clk(scanb_clk),`
`endif	`endif
`.CK(clk),`	`.CK(clk),`
`.ADR(addr),`	`.ADR(addr),`
`.DI(di),`	`.DI(di),`
`.WEN(~we),`	`.WEN(~we),`