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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32.v] - Diff between revs 1163 and 1214

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Rev 1163	Rev 1214
Line 61...	Line 61...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2003/04/07 01:19:07 lampret`
	`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
	`//`
`// Revision 1.3 2002/10/28 15:03:50 mohor`	`// Revision 1.3 2002/10/28 15:03:50 mohor`
`// Signal scanb_sen renamed to scanb_en.`	`// Signal scanb_sen renamed to scanb_en.`
`//`	`//`
`// Revision 1.2 2002/10/17 20:04:40 lampret`	`// Revision 1.2 2002/10/17 20:04:40 lampret`
`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`	`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
Line 98...	Line 101...
`include "or1200_defines.v"	`include "or1200_defines.v"

`module or1200_spram_2048x32(`	`module or1200_spram_2048x32(`
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
`endif	`endif
`// Generic synchronous single-port RAM interface`	`// Generic synchronous single-port RAM interface`
`clk, rst, ce, we, oe, addr, di, do`	`clk, rst, ce, we, oe, addr, di, do`
`);`	`);`

Line 114...	Line 117...

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`//`	`//`
`// RAM BIST`	`// RAM BIST`
`//`	`//`
`input scanb_rst,`	`input mbist_si_i;`
`scanb_si,`	input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
`scanb_en,`	`output mbist_so_o;`
`scanb_clk;`
`output scanb_so;`
`endif	`endif

`//`	`//`
`// Generic synchronous single-port RAM interface`	`// Generic synchronous single-port RAM interface`
`//`	`//`
Line 137...	Line 138...

`//`	`//`
`// Internal wires and registers`	`// Internal wires and registers`
`//`	`//`

	`ifdef OR1200_ARTISAN_SSP
	`else
`ifdef OR1200_VIRTUALSILICON_SSP	`ifdef OR1200_VIRTUALSILICON_SSP
`else	`else
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`assign scanb_so = scanb_si;`	`assign mbist_so_o = mbist_si_i;`
	`endif
`endif	`endif
`endif	`endif

`ifdef OR1200_ARTISAN_SSP	`ifdef OR1200_ARTISAN_SSP

Line 154...	Line 158...
`// Artisan Synchronous Single-Port RAM (ra1sh)`	`// Artisan Synchronous Single-Port RAM (ra1sh)`
`//`	`//`
`ifdef UNUSED	`ifdef UNUSED
`art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp(`	`art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp(`
`else	`else
`art_hdsp_2048x32 artisan_ssp(`	`ifdef OR1200_BIST
	`art_hssp_2048x32_bist artisan_ssp(`
	`else
	`art_hssp_2048x32 artisan_ssp(`
`endif	`endif
`.clk(clk),`	`endif
`.cen(~ce),`	`ifdef OR1200_BIST
`.wen(~we),`	`// RAM BIST`
`.a(addr),`	`.mbist_si_i(mbist_si_i),`
`.d(di),`	`.mbist_so_o(mbist_so_o),`
`.oen(~oe),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.q(do)`	`endif
	`.CLK(clk),`
	`.CEN(~ce),`
	`.WEN(~we),`
	`.A(addr),`
	`.D(di),`
	`.OEN(~oe),`
	`.Q(do)`
`);`	`);`

`else	`else

`ifdef OR1200_AVANT_ATP	`ifdef OR1200_AVANT_ATP
Line 225...	Line 239...
`vs_hdsp_2048x32 vs_ssp(`	`vs_hdsp_2048x32 vs_ssp(`
`endif	`endif
`endif	`endif
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_si_i),`
`.scanb_si(scanb_si),`	`.mbist_so_o(mbist_so_o),`
`.scanb_so(scanb_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif
`.CK(clk),`	`.CK(clk),`
`.ADR(addr),`	`.ADR(addr),`
`.DI(di),`	`.DI(di),`
`.WEN(~we),`	`.WEN(~we),`

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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32.v] - Diff between revs 1163 and 1214