| Line 21... |
Line 21... |
//// - Virage Single-Port Sync RAM ////
|
//// - Virage Single-Port Sync RAM ////
|
//// - Virtual Silicon Single-Port Sync RAM ////
|
//// - Virtual Silicon Single-Port Sync RAM ////
|
//// ////
|
//// ////
|
//// Supported FPGA RAMs are: ////
|
//// Supported FPGA RAMs are: ////
|
//// - Xilinx Virtex RAMB4_S16 ////
|
//// - Xilinx Virtex RAMB4_S16 ////
|
|
//// - Altera LPM ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - xilinx rams need external tri-state logic ////
|
//// - xilinx rams need external tri-state logic ////
|
//// - fix avant! two-port ram ////
|
//// - fix avant! two-port ram ////
|
//// - add additional RAMs (Altera etc) ////
|
//// - add additional RAMs ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
| Line 60... |
Line 61... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.2 2002/10/17 20:04:41 lampret
|
|
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
|
|
//
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
//
|
//
|
// Revision 1.8 2001/11/02 18:57:14 lampret
|
// Revision 1.8 2001/11/02 18:57:14 lampret
|
// Modified virtual silicon instantiations.
|
// Modified virtual silicon instantiations.
|
| Line 275... |
Line 279... |
.DO({unconnected, do[23:16]})
|
.DO({unconnected, do[23:16]})
|
);
|
);
|
|
|
`else
|
`else
|
|
|
|
`ifdef OR1200_ALTERA_LPM
|
|
|
|
//
|
|
// Instantiation of FPGA memory:
|
|
//
|
|
// Altera LPM
|
|
//
|
|
// Added By Jamil Khatib
|
|
//
|
|
|
|
wire wr;
|
|
|
|
assign wr = ce & we;
|
|
|
|
initial $display("Using Altera LPM.");
|
|
|
|
lpm_ram_dq lpm_ram_dq_component (
|
|
.address(addr),
|
|
.inclock(clk),
|
|
.outclock(clk),
|
|
.data(di),
|
|
.we(wr),
|
|
.q(do)
|
|
);
|
|
|
|
defparam lpm_ram_dq_component.lpm_width = dw,
|
|
lpm_ram_dq_component.lpm_widthad = aw,
|
|
lpm_ram_dq_component.lpm_indata = "REGISTERED",
|
|
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
|
|
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
|
|
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
|
|
// examplar attribute lpm_ram_dq_component NOOPT TRUE
|
|
|
|
`else
|
|
|
//
|
//
|
// Generic single-port synchronous RAM model
|
// Generic single-port synchronous RAM model
|
//
|
//
|
|
|
//
|
//
|
| Line 288... |
Line 327... |
reg [dw-1:0] do_reg; // RAM data output register
|
reg [dw-1:0] do_reg; // RAM data output register
|
|
|
//
|
//
|
// Data output drivers
|
// Data output drivers
|
//
|
//
|
assign do = (oe) ? do_reg : {dw{1'bz}};
|
assign do = (oe) ? do_reg : {dw{1'b0}};
|
|
|
//
|
//
|
// RAM read and write
|
// RAM read and write
|
//
|
//
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce && !we)
|
if (ce && !we)
|
do_reg <= #1 mem[addr];
|
do_reg <= #1 mem[addr];
|
else if (ce && we)
|
else if (ce && we)
|
mem[addr] <= #1 di;
|
mem[addr] <= #1 di;
|
|
|
|
`endif // !OR1200_ALTERA_LPM
|
`endif // !OR1200_XILINX_RAMB4_S16
|
`endif // !OR1200_XILINX_RAMB4_S16
|
`endif // !OR1200_VIRTUALSILICON_SSP
|
`endif // !OR1200_VIRTUALSILICON_SSP
|
`endif // !OR1200_VIRAGE_SSP
|
`endif // !OR1200_VIRAGE_SSP
|
`endif // !OR1200_AVANT_ATP
|
`endif // !OR1200_AVANT_ATP
|
`endif // !OR1200_ARTISAN_SSP
|
`endif // !OR1200_ARTISAN_SSP
|
