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Rev 663	Rev 788
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2002/02/12 01:33:47 lampret`
	`// No longer using async rst as sync reset for the counter.`
	`//`
`// Revision 1.2 2002/01/28 01:16:00 lampret`	`// Revision 1.2 2002/01/28 01:16:00 lampret`
`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`	`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
`//`	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
Line 169...	Line 172...

`//`	`//`
`// Read TT registers`	`// Read TT registers`
`//`	`//`
`always @(spr_addr or ttmr or ttcr)`	`always @(spr_addr or ttmr or ttcr)`
case (spr_addr[`OR1200_TTOFS_BITS]) // synopsys full_case parallel_case	case (spr_addr[`OR1200_TTOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_TT_READREGS	`ifdef OR1200_TT_READREGS
`OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;	`OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;
`endif	`endif
`default: spr_dat_o = ttcr;`	`default: spr_dat_o = ttcr;`
`endcase`	`endcase`

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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_tt.v] - Diff between revs 663 and 788