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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_wb_biu.v] - Diff between revs 1163 and 1171

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Rev 1163	Rev 1171
Line 47...	Line 47...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.6 2003/04/07 20:57:46 lampret`
	`// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.`
	`//`
`// Revision 1.5 2002/12/08 08:57:56 lampret`	`// Revision 1.5 2002/12/08 08:57:56 lampret`
`// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.`	`// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.`
`//`	`//`
`// Revision 1.4 2002/09/16 03:09:16 lampret`	`// Revision 1.4 2002/09/16 03:09:16 lampret`
`// Fixed a combinational loop.`	`// Fixed a combinational loop.`
Line 248...	Line 251...
`//`	`//`
`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if (rst)`	`if (rst)`
`valid_div <= #1 2'b0;`	`valid_div <= #1 2'b0;`
`else`	`else`
`valid_div <= #1 valid_div + 'd1;`	`valid_div <= #1 valid_div + 1'd1;`

`//`	`//`
`// biu_ack_o is one RISC clock cycle long long_ack_o.`	`// biu_ack_o is one RISC clock cycle long long_ack_o.`
`// long_ack_o is one, two or four RISC clock cycles long because`	`// long_ack_o is one, two or four RISC clock cycles long because`
`// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.`	`// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.`

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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_wb_biu.v] - Diff between revs 1163 and 1171