| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.25 2002/09/07 19:16:10 lampret
|
|
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
|
|
//
|
// Revision 1.24 2002/09/07 05:42:02 lampret
|
// Revision 1.24 2002/09/07 05:42:02 lampret
|
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
|
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
|
//
|
//
|
// Revision 1.23 2002/09/04 00:50:34 lampret
|
// Revision 1.23 2002/09/04 00:50:34 lampret
|
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
|
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
|
| Line 385... |
Line 388... |
// l.add/l.addi also don't set SR[CY].]
|
// l.add/l.addi also don't set SR[CY].]
|
//
|
//
|
//`define OR1200_IMPL_ADDC
|
//`define OR1200_IMPL_ADDC
|
|
|
//
|
//
|
|
// Implement optional l.div/l.divu instructions
|
|
//
|
|
// By default divide instructions are not implemented
|
|
// to save area and increase clock frequency. or32 C/C++
|
|
// compiler can use soft library for division.
|
|
//
|
|
//`define OR1200_IMPL_DIV
|
|
|
|
//
|
// Implement rotate in the ALU
|
// Implement rotate in the ALU
|
//
|
//
|
// At the time of writing this, or32
|
// At the time of writing this, or32
|
// C/C++ compiler doesn't generate rotate
|
// C/C++ compiler doesn't generate rotate
|
// instructions. However or32 assembler
|
// instructions. However or32 assembler
|
| Line 444... |
Line 456... |
//
|
//
|
`define OR1200_IMPL_MEM2REG1
|
`define OR1200_IMPL_MEM2REG1
|
//`define OR1200_IMPL_MEM2REG2
|
//`define OR1200_IMPL_MEM2REG2
|
|
|
//
|
//
|
// Simulate l.div and l.divu
|
|
//
|
|
// If commented, l.div/l.divu will produce undefined result. If enabled,
|
|
// div instructions will be simulated, but not synthesized ! OR1200
|
|
// does not have a hardware divider.
|
|
//
|
|
`define OR1200_SIM_ALU_DIV
|
|
`define OR1200_SIM_ALU_DIVU
|
|
|
|
//
|
|
// ALUOPs
|
// ALUOPs
|
//
|
//
|
`define OR1200_ALUOP_WIDTH 4
|
`define OR1200_ALUOP_WIDTH 4
|
`define OR1200_ALUOP_NOP 4'd4
|
`define OR1200_ALUOP_NOP 4'd4
|
/* Order defined by arith insns that have two source operands both in regs
|
/* Order defined by arith insns that have two source operands both in regs
|
