| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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`include "defines.v"
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`include "defines.v"
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|
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module cfgr(
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module cfgr(
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// RISC Internal Interface
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// RISC Internal Interface
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clk, rst, spr_addr, spr_dat_o
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clk, rst, spr_addr, spr_dat_o
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| Line 79... |
Line 84... |
`ifdef SYS_FULL_DECODE
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`ifdef SYS_FULL_DECODE
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if (!spr_addr[31:4])
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if (!spr_addr[31:4])
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`endif
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`endif
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case(spr_addr[3:0])
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case(spr_addr[3:0])
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`SPRGRP_SYS_VR: begin
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`SPRGRP_SYS_VR: begin
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spr_dat_o[`VR_REV_BITS] <= `VR_REV;
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spr_dat_o[`VR_REV_BITS] = `VR_REV;
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spr_dat_o[`VR_RES1_BITS] <= `VR_RES1;
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spr_dat_o[`VR_RES1_BITS] = `VR_RES1;
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spr_dat_o[`VR_CFG_BITS] <= `VR_CFG;
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spr_dat_o[`VR_CFG_BITS] = `VR_CFG;
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spr_dat_o[`VR_VER_BITS] <= `VR_VER;
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spr_dat_o[`VR_VER_BITS] = `VR_VER;
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end
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end
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`SPRGRP_SYS_UPR: begin
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`SPRGRP_SYS_UPR: begin
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spr_dat_o[`UPR_UP_BITS] <= `UPR_UP;
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spr_dat_o[`UPR_UP_BITS] = `UPR_UP;
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spr_dat_o[`UPR_DCP_BITS] <= `UPR_DCP;
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spr_dat_o[`UPR_DCP_BITS] = `UPR_DCP;
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spr_dat_o[`UPR_ICP_BITS] <= `UPR_ICP;
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spr_dat_o[`UPR_ICP_BITS] = `UPR_ICP;
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spr_dat_o[`UPR_DMP_BITS] <= `UPR_DMP;
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spr_dat_o[`UPR_DMP_BITS] = `UPR_DMP;
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spr_dat_o[`UPR_IMP_BITS] <= `UPR_IMP;
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spr_dat_o[`UPR_IMP_BITS] = `UPR_IMP;
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spr_dat_o[`UPR_MP_BITS] <= `UPR_MP;
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spr_dat_o[`UPR_MP_BITS] = `UPR_MP;
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spr_dat_o[`UPR_DUP_BITS] <= `UPR_DUP;
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spr_dat_o[`UPR_DUP_BITS] = `UPR_DUP;
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spr_dat_o[`UPR_PCUP_BITS] <= `UPR_PCUP;
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spr_dat_o[`UPR_PCUP_BITS] = `UPR_PCUP;
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spr_dat_o[`UPR_PMP_BITS] <= `UPR_PMP;
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spr_dat_o[`UPR_PMP_BITS] = `UPR_PMP;
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spr_dat_o[`UPR_PICP_BITS] <= `UPR_PICP;
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spr_dat_o[`UPR_PICP_BITS] = `UPR_PICP;
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spr_dat_o[`UPR_TTP_BITS] <= `UPR_TTP;
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spr_dat_o[`UPR_TTP_BITS] = `UPR_TTP;
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spr_dat_o[`UPR_RES1_BITS] <= `UPR_RES1;
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spr_dat_o[`UPR_RES1_BITS] = `UPR_RES1;
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spr_dat_o[`UPR_CUP_BITS] <= `UPR_CUP;
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spr_dat_o[`UPR_CUP_BITS] = `UPR_CUP;
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end
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end
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`SPRGRP_SYS_CPUCFGR: begin
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`SPRGRP_SYS_CPUCFGR: begin
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spr_dat_o[`CPUCFGR_NSGF_BITS] <= `CPUCFGR_NSGF;
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spr_dat_o[`CPUCFGR_NSGF_BITS] = `CPUCFGR_NSGF;
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spr_dat_o[`CPUCFGR_HGF_BITS] <= `CPUCFGR_HGF;
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spr_dat_o[`CPUCFGR_HGF_BITS] = `CPUCFGR_HGF;
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spr_dat_o[`CPUCFGR_OB32S_BITS] <= `CPUCFGR_OB32S;
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spr_dat_o[`CPUCFGR_OB32S_BITS] = `CPUCFGR_OB32S;
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spr_dat_o[`CPUCFGR_OB64S_BITS] <= `CPUCFGR_OB64S;
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spr_dat_o[`CPUCFGR_OB64S_BITS] = `CPUCFGR_OB64S;
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spr_dat_o[`CPUCFGR_OF32S_BITS] <= `CPUCFGR_OF32S;
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spr_dat_o[`CPUCFGR_OF32S_BITS] = `CPUCFGR_OF32S;
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spr_dat_o[`CPUCFGR_OF64S_BITS] <= `CPUCFGR_OF64S;
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spr_dat_o[`CPUCFGR_OF64S_BITS] = `CPUCFGR_OF64S;
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spr_dat_o[`CPUCFGR_OV64S_BITS] <= `CPUCFGR_OV64S;
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spr_dat_o[`CPUCFGR_OV64S_BITS] = `CPUCFGR_OV64S;
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spr_dat_o[`CPUCFGR_RES1_BITS] <= `CPUCFGR_RES1;
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spr_dat_o[`CPUCFGR_RES1_BITS] = `CPUCFGR_RES1;
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end
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end
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`SPRGRP_SYS_DMMUCFGR: begin
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`SPRGRP_SYS_DMMUCFGR: begin
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spr_dat_o[`DMMUCFGR_NTW_BITS] <= `DMMUCFGR_NTW;
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spr_dat_o[`DMMUCFGR_NTW_BITS] = `DMMUCFGR_NTW;
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spr_dat_o[`DMMUCFGR_NTS_BITS] <= `DMMUCFGR_NTS;
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spr_dat_o[`DMMUCFGR_NTS_BITS] = `DMMUCFGR_NTS;
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spr_dat_o[`DMMUCFGR_NAE_BITS] <= `DMMUCFGR_NAE;
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spr_dat_o[`DMMUCFGR_NAE_BITS] = `DMMUCFGR_NAE;
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spr_dat_o[`DMMUCFGR_CRI_BITS] <= `DMMUCFGR_CRI;
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spr_dat_o[`DMMUCFGR_CRI_BITS] = `DMMUCFGR_CRI;
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spr_dat_o[`DMMUCFGR_PRI_BITS] <= `DMMUCFGR_PRI;
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spr_dat_o[`DMMUCFGR_PRI_BITS] = `DMMUCFGR_PRI;
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spr_dat_o[`DMMUCFGR_TEIRI_BITS] <= `DMMUCFGR_TEIRI;
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spr_dat_o[`DMMUCFGR_TEIRI_BITS] = `DMMUCFGR_TEIRI;
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spr_dat_o[`DMMUCFGR_HTR_BITS] <= `DMMUCFGR_HTR;
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spr_dat_o[`DMMUCFGR_HTR_BITS] = `DMMUCFGR_HTR;
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spr_dat_o[`DMMUCFGR_RES1_BITS] <= `DMMUCFGR_RES1;
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spr_dat_o[`DMMUCFGR_RES1_BITS] = `DMMUCFGR_RES1;
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end
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end
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`SPRGRP_SYS_IMMUCFGR: begin
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`SPRGRP_SYS_IMMUCFGR: begin
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spr_dat_o[`IMMUCFGR_NTW_BITS] <= `IMMUCFGR_NTW;
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spr_dat_o[`IMMUCFGR_NTW_BITS] = `IMMUCFGR_NTW;
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spr_dat_o[`IMMUCFGR_NTS_BITS] <= `IMMUCFGR_NTS;
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spr_dat_o[`IMMUCFGR_NTS_BITS] = `IMMUCFGR_NTS;
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spr_dat_o[`IMMUCFGR_NAE_BITS] <= `IMMUCFGR_NAE;
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spr_dat_o[`IMMUCFGR_NAE_BITS] = `IMMUCFGR_NAE;
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spr_dat_o[`IMMUCFGR_CRI_BITS] <= `IMMUCFGR_CRI;
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spr_dat_o[`IMMUCFGR_CRI_BITS] = `IMMUCFGR_CRI;
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spr_dat_o[`IMMUCFGR_PRI_BITS] <= `IMMUCFGR_PRI;
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spr_dat_o[`IMMUCFGR_PRI_BITS] = `IMMUCFGR_PRI;
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spr_dat_o[`IMMUCFGR_TEIRI_BITS] <= `IMMUCFGR_TEIRI;
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spr_dat_o[`IMMUCFGR_TEIRI_BITS] = `IMMUCFGR_TEIRI;
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spr_dat_o[`IMMUCFGR_HTR_BITS] <= `IMMUCFGR_HTR;
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spr_dat_o[`IMMUCFGR_HTR_BITS] = `IMMUCFGR_HTR;
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spr_dat_o[`IMMUCFGR_RES1_BITS] <= `IMMUCFGR_RES1;
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spr_dat_o[`IMMUCFGR_RES1_BITS] = `IMMUCFGR_RES1;
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end
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end
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`SPRGRP_SYS_DCCFGR: begin
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`SPRGRP_SYS_DCCFGR: begin
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spr_dat_o[`DCCFGR_NCW_BITS] <= `DCCFGR_NCW;
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spr_dat_o[`DCCFGR_NCW_BITS] = `DCCFGR_NCW;
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spr_dat_o[`DCCFGR_NCS_BITS] <= `DCCFGR_NCS;
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spr_dat_o[`DCCFGR_NCS_BITS] = `DCCFGR_NCS;
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spr_dat_o[`DCCFGR_CBS_BITS] <= `DCCFGR_CBS;
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spr_dat_o[`DCCFGR_CBS_BITS] = `DCCFGR_CBS;
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spr_dat_o[`DCCFGR_CWS_BITS] <= `DCCFGR_CWS;
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spr_dat_o[`DCCFGR_CWS_BITS] = `DCCFGR_CWS;
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spr_dat_o[`DCCFGR_CCRI_BITS] <= `DCCFGR_CCRI;
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spr_dat_o[`DCCFGR_CCRI_BITS] = `DCCFGR_CCRI;
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spr_dat_o[`DCCFGR_CBIRI_BITS] <= `DCCFGR_CBIRI;
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spr_dat_o[`DCCFGR_CBIRI_BITS] = `DCCFGR_CBIRI;
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spr_dat_o[`DCCFGR_CBPRI_BITS] <= `DCCFGR_CBPRI;
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spr_dat_o[`DCCFGR_CBPRI_BITS] = `DCCFGR_CBPRI;
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spr_dat_o[`DCCFGR_CBLRI_BITS] <= `DCCFGR_CBLRI;
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spr_dat_o[`DCCFGR_CBLRI_BITS] = `DCCFGR_CBLRI;
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spr_dat_o[`DCCFGR_CBFRI_BITS] <= `DCCFGR_CBFRI;
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spr_dat_o[`DCCFGR_CBFRI_BITS] = `DCCFGR_CBFRI;
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spr_dat_o[`DCCFGR_CBWBRI_BITS] <= `DCCFGR_CBWBRI;
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spr_dat_o[`DCCFGR_CBWBRI_BITS] = `DCCFGR_CBWBRI;
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spr_dat_o[`DCCFGR_RES1_BITS] <= `DCCFGR_RES1;
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spr_dat_o[`DCCFGR_RES1_BITS] = `DCCFGR_RES1;
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end
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end
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`SPRGRP_SYS_ICCFGR: begin
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`SPRGRP_SYS_ICCFGR: begin
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spr_dat_o[`ICCFGR_NCW_BITS] <= `ICCFGR_NCW;
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spr_dat_o[`ICCFGR_NCW_BITS] = `ICCFGR_NCW;
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spr_dat_o[`ICCFGR_NCS_BITS] <= `ICCFGR_NCS;
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spr_dat_o[`ICCFGR_NCS_BITS] = `ICCFGR_NCS;
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spr_dat_o[`ICCFGR_CBS_BITS] <= `ICCFGR_CBS;
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spr_dat_o[`ICCFGR_CBS_BITS] = `ICCFGR_CBS;
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spr_dat_o[`ICCFGR_CWS_BITS] <= `ICCFGR_CWS;
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spr_dat_o[`ICCFGR_CWS_BITS] = `ICCFGR_CWS;
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spr_dat_o[`ICCFGR_CCRI_BITS] <= `ICCFGR_CCRI;
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spr_dat_o[`ICCFGR_CCRI_BITS] = `ICCFGR_CCRI;
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spr_dat_o[`ICCFGR_CBIRI_BITS] <= `ICCFGR_CBIRI;
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spr_dat_o[`ICCFGR_CBIRI_BITS] = `ICCFGR_CBIRI;
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spr_dat_o[`ICCFGR_CBPRI_BITS] <= `ICCFGR_CBPRI;
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spr_dat_o[`ICCFGR_CBPRI_BITS] = `ICCFGR_CBPRI;
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spr_dat_o[`ICCFGR_CBLRI_BITS] <= `ICCFGR_CBLRI;
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spr_dat_o[`ICCFGR_CBLRI_BITS] = `ICCFGR_CBLRI;
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spr_dat_o[`ICCFGR_CBFRI_BITS] <= `ICCFGR_CBFRI;
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spr_dat_o[`ICCFGR_CBFRI_BITS] = `ICCFGR_CBFRI;
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spr_dat_o[`ICCFGR_CBWBRI_BITS] <= `ICCFGR_CBWBRI;
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spr_dat_o[`ICCFGR_CBWBRI_BITS] = `ICCFGR_CBWBRI;
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spr_dat_o[`ICCFGR_RES1_BITS] <= `ICCFGR_RES1;
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spr_dat_o[`ICCFGR_RES1_BITS] = `ICCFGR_RES1;
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end
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end
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`SPRGRP_SYS_DCFGR: begin
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`SPRGRP_SYS_DCFGR: begin
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spr_dat_o[`DCFGR_NDP_BITS] <= `DCFGR_NDP;
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spr_dat_o[`DCFGR_NDP_BITS] = `DCFGR_NDP;
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spr_dat_o[`DCFGR_WPCI_BITS] <= `DCFGR_WPCI;
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spr_dat_o[`DCFGR_WPCI_BITS] = `DCFGR_WPCI;
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spr_dat_o[`DCFGR_RES1_BITS] <= `DCFGR_RES1;
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spr_dat_o[`DCFGR_RES1_BITS] = `DCFGR_RES1;
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end
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end
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default: spr_dat_o <= 32'b0;
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default: spr_dat_o = 32'h0000_0000;
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endcase
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endcase
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`ifdef SYS_FULL_DECODE
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else
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spr_dat_o = 32'h0000_0000;
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`endif
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|
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`else
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`else
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//
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//
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// When configuration registers are not implemented, only
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// When configuration registers are not implemented, only
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// implement VR and UPR
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// implement VR and UPR
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| Line 174... |
Line 184... |
`ifdef SYS_FULL_DECODE
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`ifdef SYS_FULL_DECODE
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if (!spr_addr[31:4])
|
if (!spr_addr[31:4])
|
`endif
|
`endif
|
case(spr_addr[3:0])
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case(spr_addr[3:0])
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`SPRGRP_SYS_VR: begin
|
`SPRGRP_SYS_VR: begin
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spr_dat_o[`VR_REV_BITS] <= `VR_REV;
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spr_dat_o[`VR_REV_BITS] = `VR_REV;
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spr_dat_o[`VR_RES1_BITS] <= `VR_RES1;
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spr_dat_o[`VR_RES1_BITS] = `VR_RES1;
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spr_dat_o[`VR_CFG_BITS] <= `VR_CFG;
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spr_dat_o[`VR_CFG_BITS] = `VR_CFG;
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spr_dat_o[`VR_VER_BITS] <= `VR_VER;
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spr_dat_o[`VR_VER_BITS] = `VR_VER;
|
end
|
end
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`SPRGRP_SYS_UPR: begin
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`SPRGRP_SYS_UPR: begin
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spr_dat_o[`UPR_UP_BITS] <= `UPR_UP;
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spr_dat_o[`UPR_UP_BITS] = `UPR_UP;
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spr_dat_o[`UPR_DCP_BITS] <= `UPR_DCP;
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spr_dat_o[`UPR_DCP_BITS] = `UPR_DCP;
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spr_dat_o[`UPR_ICP_BITS] <= `UPR_ICP;
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spr_dat_o[`UPR_ICP_BITS] = `UPR_ICP;
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spr_dat_o[`UPR_DMP_BITS] <= `UPR_DMP;
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spr_dat_o[`UPR_DMP_BITS] = `UPR_DMP;
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spr_dat_o[`UPR_IMP_BITS] <= `UPR_IMP;
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spr_dat_o[`UPR_IMP_BITS] = `UPR_IMP;
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spr_dat_o[`UPR_MP_BITS] <= `UPR_MP;
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spr_dat_o[`UPR_MP_BITS] = `UPR_MP;
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spr_dat_o[`UPR_DUP_BITS] <= `UPR_DUP;
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spr_dat_o[`UPR_DUP_BITS] = `UPR_DUP;
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spr_dat_o[`UPR_PCUP_BITS] <= `UPR_PCUP;
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spr_dat_o[`UPR_PCUP_BITS] = `UPR_PCUP;
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spr_dat_o[`UPR_PMP_BITS] <= `UPR_PMP;
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spr_dat_o[`UPR_PMP_BITS] = `UPR_PMP;
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spr_dat_o[`UPR_PICP_BITS] <= `UPR_PICP;
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spr_dat_o[`UPR_PICP_BITS] = `UPR_PICP;
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spr_dat_o[`UPR_TTP_BITS] <= `UPR_TTP;
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spr_dat_o[`UPR_TTP_BITS] = `UPR_TTP;
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spr_dat_o[`UPR_RES1_BITS] <= `UPR_RES1;
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spr_dat_o[`UPR_RES1_BITS] = `UPR_RES1;
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spr_dat_o[`UPR_CUP_BITS] <= `UPR_CUP;
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spr_dat_o[`UPR_CUP_BITS] = `UPR_CUP;
|
end
|
end
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default: spr_dat_o <= 32'b0;
|
default: spr_dat_o = 32'h0000_0000;
|
endcase
|
endcase
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`ifdef SYS_FULL_DECODE
|
|
else
|
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spr_dat_o = 32'h0000_0000;
|
|
`endif
|
|
|
`endif
|
`endif
|
|
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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