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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [cpu.v] - Diff between revs 176 and 203

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Rev 176	Rev 203
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2001/08/17 08:01:19 lampret`
	`// IC enable/disable.`
	`//`
`// Revision 1.3 2001/08/13 03:36:20 lampret`	`// Revision 1.3 2001/08/13 03:36:20 lampret`
`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`	`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
`//`	`//`
`// Revision 1.2 2001/08/09 13:39:33 lampret`	`// Revision 1.2 2001/08/09 13:39:33 lampret`
`// Major clean-up.`	`// Major clean-up.`
Line 54...	Line 57...
`// Revision 1.1 2001/07/20 00:46:03 lampret`	`// Revision 1.1 2001/07/20 00:46:03 lampret`
`// Development version of RTL. Libraries are missing.`	`// Development version of RTL. Libraries are missing.`
`//`	`//`
`//`	`//`

	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
	`// synopsys translate_on`
`include "defines.v"	`include "defines.v"

`module cpu(`	`module cpu(`
`// Clk & Rst`	`// Clk & Rst`
`clk, rst,`	`clk, rst,`

`// Insn interface`	`// Insn interface`
`ic_insn, ic_pcaddr, ic_stall, ic_en,`	`ic_insn, ic_addr, ic_stall, ic_fetchop, ic_en,`
	`immu_en, immuexcept_miss, immuexcept_fault,`

`// Trace port`	`// Trace port`
`tp_dir_in, tp_sel, tp_in, tp_out,`	`tp_dir_in, tp_sel, tp_in, tp_out,`

`// Data interface`	`// Data interface`
`dclsu_stall, dclsu_addr, dclsu_datain, dclsu_dataout, dclsu_lsuop, dc_en,`	`dclsu_stall, dclsu_unstall, dclsu_addr, dclsu_datain, dclsu_dataout, dclsu_lsuop, dc_en,`
	`dmmu_en, dmmuexcept_miss, dmmuexcept_fault,`

`// Interrupt exceptions`	`// Interrupt exceptions`
`int_high, int_low,`	`int_high, int_low,`

`// SPR interface`	`// SPR interface`
`spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm, spr_cs, spr_we,`	`supv, spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm, spr_dat_dmmu, spr_cs, spr_we,`

`// Trace port`	`// Trace port`
`tp2w, tp3w`	`tp2w, tp3w`
`);`	`);`

Line 97...	Line 104...

`//`	`//`
`// Insn (IC) interface`	`// Insn (IC) interface`
`//`	`//`
`input [31:0] ic_insn;`	`input [31:0] ic_insn;`
`output [31:0] ic_pcaddr;`	`output [31:0] ic_addr;`
`input ic_stall;`	`input ic_stall;`
	output [`FETCHOP_WIDTH-1:0] ic_fetchop;
`output ic_en;`	`output ic_en;`

`//`	`//`
	`// Insn (IMMU) interface`
	`//`
	`input immuexcept_miss;`
	`input immuexcept_fault;`
	`output immu_en;`

	`//`
`// Trace`	`// Trace`
`//`	`//`
`input tp_dir_in;`	`input tp_dir_in;`
`input [1:0] tp_sel;`	`input [1:0] tp_sel;`
`input [31:0] tp_in;`	`input [31:0] tp_in;`
Line 115...	Line 130...

`//`	`//`
`// Data (DC) interface`	`// Data (DC) interface`
`//`	`//`
`input dclsu_stall;`	`input dclsu_stall;`
	`input dclsu_unstall;`
`output [31:0] dclsu_addr;`	`output [31:0] dclsu_addr;`
`input [31:0] dclsu_datain;`	`input [31:0] dclsu_datain;`
`output [31:0] dclsu_dataout;`	`output [31:0] dclsu_dataout;`
output [`LSUOP_WIDTH-1:0] dclsu_lsuop;	output [`LSUOP_WIDTH-1:0] dclsu_lsuop;
`output dc_en;`	`output dc_en;`

`//`	`//`
	`// Data (DMMU) interface`
	`//`
	`input dmmuexcept_miss;`
	`input dmmuexcept_fault;`
	`output dmmu_en;`

	`//`
`// SPR interface`	`// SPR interface`
`//`	`//`
	`input supv;`
`input [dw-1:0] spr_dat_pic;`	`input [dw-1:0] spr_dat_pic;`
`input [dw-1:0] spr_dat_tt;`	`input [dw-1:0] spr_dat_tt;`
`input [dw-1:0] spr_dat_pm;`	`input [dw-1:0] spr_dat_pm;`
	`input [dw-1:0] spr_dat_dmmu;`
`output [dw-1:0] spr_addr;`	`output [dw-1:0] spr_addr;`
`output [dw-1:0] spr_dataout;`	`output [dw-1:0] spr_dataout;`
`output [31:0] spr_cs;`	`output [31:0] spr_cs;`
`output spr_we;`	`output spr_we;`

Line 193...	Line 218...
`wire [31:0] tp_insn;`	`wire [31:0] tp_insn;`
`wire tp_wr_insn;`	`wire tp_wr_insn;`
`wire [15:0] spr_addrimm;`	`wire [15:0] spr_addrimm;`
`wire sig_syscall;`	`wire sig_syscall;`
`wire [31:0] spr_dat_cfgr;`	`wire [31:0] spr_dat_cfgr;`
	`wire force_dslot_fetch;`
	`wire if_stall;`

`//`	`//`
`// Trace port`	`// Trace port`
`//`	`//`
`wire [31:0] rfa_tqa;`	`wire [31:0] rfa_tqa;`
Line 211...	Line 238...
assign dc_en = sr[`SR_DCE];	assign dc_en = sr[`SR_DCE];

`//`	`//`
`// Instruction cache enable`	`// Instruction cache enable`
`//`	`//`
	`//assign ic_en = 1'b1;`
assign ic_en = sr[`SR_ICE];	assign ic_en = sr[`SR_ICE];

`//`	`//`
	`// DMMU enable`
	`//`
	assign dmmu_en = sr[`SR_DME];

	`//`
	`// IMMU enable`
	`//`
	assign immu_en = sr[`SR_IME];

	`//`
	`// SUPV bit`
	`//`
	assign supv = sr[`SR_SUPV];

	`//`
`// Instantiation of exception block`	`// Instantiation of exception block`
`//`	`//`
`except except(`	`except except(`
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.sig_dtlbmiss(1'b0),`	`.sig_dtlbmiss(dmmuexcept_miss),`
`.sig_dmmufault(1'b0),`	`.sig_dmmufault(dmmuexcept_fault),`
`.sig_inthigh(int_high),`	`.sig_inthigh(int_high),`
`.sig_syscall(sig_syscall),`	`.sig_syscall(sig_syscall),`
`.sig_itlbmiss(1'b0),`	`.sig_itlbmiss(immuexcept_miss),`
`.sig_immufault(1'b0),`	`.sig_immufault(immuexcept_fault),`
`.sig_intlow(int_low),`	`.sig_intlow(int_low),`
`.branch_taken(branch_taken),`	`.branch_taken(branch_taken),`
`.pipeline_freeze(pipeline_freeze),`	`.pipeline_freeze(pipeline_freeze),`
`.ic_stall(ic_stall),`	`.if_stall(if_stall),`
`.if_pc(if_pc),`	`.if_pc(if_pc),`
`.lr_sav(lr_sav),`	`.lr_sav(lr_sav),`
`.except_flushpipe(except_flushpipe),`	`.except_flushpipe(except_flushpipe),`
`.except_type(except_type),`	`.except_type(except_type),`
`.except_start(except_start),`	`.except_start(except_start),`
Line 256...	Line 299...
`//`	`//`
`ifetch ifetch(`	`ifetch ifetch(`
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ic_insn(ic_insn),`	`.ic_insn(ic_insn),`
`.ic_pcaddr(ic_pcaddr),`	`.ic_addr(ic_addr),`
`.ic_stall(ic_stall),`	`.ic_stall(ic_stall),`
	`.ic_fetchop(ic_fetchop),`
`.tp_insn(tp_insn),`	`.tp_insn(tp_insn),`
`.tp_wr_insn(tp_wr_insn),`	`.tp_wr_insn(tp_wr_insn),`
`.pipeline_freeze(pipeline_freeze),`	`.pipeline_freeze(pipeline_freeze),`
`.if_insn(insn),`	`.if_insn(insn),`
`.if_pc(if_pc),`	`.if_pc(if_pc),`
Line 271...	Line 315...
`.branch_addrofs(branch_addrofs),`	`.branch_addrofs(branch_addrofs),`
`.lr_restor(operand_b),`	`.lr_restor(operand_b),`
`.flag(flag),`	`.flag(flag),`
`.taken(branch_taken),`	`.taken(branch_taken),`
`.binsn_addr(lr_sav),`	`.binsn_addr(lr_sav),`
`.epcr(epcr)`	`.epcr(epcr),`
	`.force_dslot_fetch(force_dslot_fetch),`
	`.if_stall(if_stall),`
	`.branch_stall(branch_stall)`
`);`	`);`

`//`	`//`
`// Instantiation of instruction decode/control logic`	`// Instantiation of instruction decode/control logic`
`//`	`//`
Line 299...	Line 346...
`.lsu_addrofs(lsu_addrofs),`	`.lsu_addrofs(lsu_addrofs),`
`.sel_a(sel_a),`	`.sel_a(sel_a),`
`.sel_b(sel_b),`	`.sel_b(sel_b),`
`.lsu_op(lsu_op),`	`.lsu_op(lsu_op),`
`.multicycle(multicycle),`	`.multicycle(multicycle),`
`.branch_stall(branch_stall),`
`.spr_addrimm(spr_addrimm),`	`.spr_addrimm(spr_addrimm),`
`.wbforw_valid(wbforw_valid),`	`.wbforw_valid(wbforw_valid),`
`.sig_syscall(sig_syscall)`	`.sig_syscall(sig_syscall),`
	`.force_dslot_fetch(force_dslot_fetch)`
`);`	`);`

`//`	`//`
`// Instantiation of write-back muxes`	`// Instantiation of write-back muxes`
`//`	`//`
Line 394...	Line 441...

`.spr_addr(spr_addr),`	`.spr_addr(spr_addr),`
`.spr_dat_pic(spr_dat_pic),`	`.spr_dat_pic(spr_dat_pic),`
`.spr_dat_tt(spr_dat_tt),`	`.spr_dat_tt(spr_dat_tt),`
`.spr_dat_pm(spr_dat_pm),`	`.spr_dat_pm(spr_dat_pm),`
	`.spr_dat_cfgr(spr_dat_cfgr),`
	`.spr_dat_dmmu(spr_dat_dmmu),`
`.spr_dataout(spr_dataout),`	`.spr_dataout(spr_dataout),`
`.spr_cs(spr_cs),`	`.spr_cs(spr_cs),`
`.spr_we(spr_we),`	`.spr_we(spr_we),`

`.epcr_we(epcr_we),`	`.epcr_we(epcr_we),`
Line 439...	Line 488...
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.multicycle(multicycle),`	`.multicycle(multicycle),`
`.except_flushpipe(except_flushpipe),`	`.except_flushpipe(except_flushpipe),`
`.lsu_stall(lsu_stall),`	`.lsu_stall(lsu_stall),`
`.ic_stall(ic_stall),`	`.if_stall(if_stall),`
	`.dclsu_unstall(dclsu_unstall),`
`.branch_stall(branch_stall),`	`.branch_stall(branch_stall),`
	`.force_dslot_fetch(force_dslot_fetch),`
`.pipeline_freeze(pipeline_freeze)`	`.pipeline_freeze(pipeline_freeze)`
`);`	`);`

`//`	`//`
`// Instantiation of configuration registers`	`// Instantiation of configuration registers`
Line 479...	Line 530...
`// To RISC core`	`// To RISC core`
`.wr_insn(tp_wr_insn),`	`.wr_insn(tp_wr_insn),`
`.insn(tp_insn),`	`.insn(tp_insn),`
`.tp1w(tp1w),`	`.tp1w(tp1w),`
`.tp2w(tp2w),`	`.tp2w(tp2w),`
`.tp3w(tp3w)`	`.tp3w(tp3w),`
	`.tp4w(),`
	`.tpdw()`
`);`	`);`

`endmodule`	`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [cpu.v] - Diff between revs 176 and 203