| Line 71... |
Line 71... |
// Insn interface
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// Insn interface
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ic_insn, ic_addr, ic_stall, ic_fetchop, ic_en,
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ic_insn, ic_addr, ic_stall, ic_fetchop, ic_en,
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immu_en, immuexcept_miss, immuexcept_fault,
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immu_en, immuexcept_miss, immuexcept_fault,
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|
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// Debug unit
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// Debug unit
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du_stall, du_addr, du_dat_du, du_read, du_write,
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du_stall, du_addr, du_dat_du, du_read, du_write, du_except,
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|
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// Data interface
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// Data interface
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dclsu_stall, dclsu_unstall, dclsu_addr, dclsu_datain, dclsu_dataout, dclsu_lsuop, dc_en,
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dclsu_stall, dclsu_unstall, dclsu_addr, dclsu_datain, dclsu_dataout, dclsu_lsuop, dc_en,
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dmmu_en, dmmuexcept_miss, dmmuexcept_fault,
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dmmu_en, dmmuexcept_miss, dmmuexcept_fault,
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|
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| Line 122... |
Line 122... |
input du_stall;
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input du_stall;
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input [dw-1:0] du_addr;
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input [dw-1:0] du_addr;
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input [dw-1:0] du_dat_du;
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input [dw-1:0] du_dat_du;
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input du_read;
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input du_read;
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input du_write;
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input du_write;
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output [`EXCEPT_WIDTH-1:0] du_except;
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|
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//
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//
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// Data (DC) interface
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// Data (DC) interface
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//
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//
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input dclsu_stall;
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input dclsu_stall;
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| Line 217... |
Line 218... |
wire except_started;
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wire except_started;
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wire [31:0] wb_pc;
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wire [31:0] wb_pc;
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wire [31:0] wb_insn;
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wire [31:0] wb_insn;
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wire [15:0] spr_addrimm;
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wire [15:0] spr_addrimm;
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wire sig_syscall;
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wire sig_syscall;
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wire sig_trap;
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wire [31:0] spr_dat_cfgr;
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wire [31:0] spr_dat_cfgr;
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wire [31:0] spr_dat_rf;
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wire [31:0] spr_dat_rf;
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wire force_dslot_fetch;
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wire force_dslot_fetch;
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wire if_stall;
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wire if_stall;
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wire id_macrc_op;
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wire id_macrc_op;
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wire ex_macrc_op;
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wire ex_macrc_op;
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wire [31:0] mult_mac_result;
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wire [31:0] mult_mac_result;
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wire mac_stall;
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wire mac_stall;
|
|
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//
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//
|
|
// Exception type going to debug unit
|
|
//
|
|
assign du_except = except_type;
|
|
|
|
//
|
// Data cache enable
|
// Data cache enable
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//
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//
|
|
//assign dc_en = 1'b1;
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assign dc_en = sr[`SR_DCE];
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assign dc_en = sr[`SR_DCE];
|
|
|
//
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//
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// Instruction cache enable
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// Instruction cache enable
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//
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//
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| Line 258... |
Line 266... |
// Instantiation of exception block
|
// Instantiation of exception block
|
//
|
//
|
except except(
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except except(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
|
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.sig_buserr(1'b0),
|
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.sig_illegal(1'b0),
|
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.sig_align(1'b0),
|
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.sig_range(1'b0),
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.sig_dtlbmiss(dmmuexcept_miss),
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.sig_dtlbmiss(dmmuexcept_miss),
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.sig_dmmufault(dmmuexcept_fault),
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.sig_dmmufault(dmmuexcept_fault),
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.sig_inthigh(int_high),
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.sig_inthigh(int_high),
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.sig_syscall(sig_syscall),
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.sig_syscall(sig_syscall),
|
|
.sig_trap(sig_trap),
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.sig_itlbmiss(immuexcept_miss),
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.sig_itlbmiss(immuexcept_miss),
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.sig_immufault(immuexcept_fault),
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.sig_immufault(immuexcept_fault),
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.sig_intlow(int_low),
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.sig_intlow(int_low),
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.branch_taken(branch_taken),
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.branch_taken(branch_taken),
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.id_freeze(id_freeze),
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.id_freeze(id_freeze),
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| Line 347... |
Line 360... |
.lsu_op(lsu_op),
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.lsu_op(lsu_op),
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.multicycle(multicycle),
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.multicycle(multicycle),
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.spr_addrimm(spr_addrimm),
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.spr_addrimm(spr_addrimm),
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.wbforw_valid(wbforw_valid),
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.wbforw_valid(wbforw_valid),
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.sig_syscall(sig_syscall),
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.sig_syscall(sig_syscall),
|
|
.sig_trap(sig_trap),
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.force_dslot_fetch(force_dslot_fetch),
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.force_dslot_fetch(force_dslot_fetch),
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.id_macrc_op(id_macrc_op),
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.id_macrc_op(id_macrc_op),
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.ex_macrc_op(ex_macrc_op)
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.ex_macrc_op(ex_macrc_op)
|
);
|
);
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|
|
