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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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`include "general.h"
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`include "general.h"
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// Data cache
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// Data cache
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module dc(clk, rst, clkdiv_by_2, dcbiu_rdy, dclsu_addr, dclsu_lsuop, dclsu_datain, dcbiu_datain,
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module dc(clk, rst, clkdiv_by_2, dcbiu_rdy, dclsu_addr, dclsu_lsuop, dclsu_datain, dcbiu_datain,
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dclsu_dataout, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dclsu_stall,
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dclsu_dataout, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dclsu_stall, dcbiu_sel,
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tp2w, tp3w, tpdw
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tp2w, tp3w, tpdw
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);
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);
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parameter dw = `OPERAND_WIDTH;
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parameter dw = `OPERAND_WIDTH;
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Line 73... |
output [dw-1:0] dcbiu_dataout;
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output [dw-1:0] dcbiu_dataout;
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output [31:0] dcbiu_addr;
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output [31:0] dcbiu_addr;
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output dcbiu_read;
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output dcbiu_read;
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output dcbiu_write;
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output dcbiu_write;
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output dclsu_stall;
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output dclsu_stall;
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output [3:0] dcbiu_sel;
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input [`TP2W_WIDTH-1:0] tp2w;
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input [`TP2W_WIDTH-1:0] tp2w;
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input [`TP3W_WIDTH-1:0] tp3w;
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input [`TP3W_WIDTH-1:0] tp3w;
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input [31:0] tpdw;
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input [31:0] tpdw;
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wire [31:0] dc_addr;
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wire [31:0] dc_addr;
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wire refill_first;
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wire refill_first;
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wire refill_prepare;
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wire refill_prepare;
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wire refill_start;
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wire refill_start;
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wire refill_rest;
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wire refill_rest;
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wire [`LSUOP_WIDTH-1:0] dcfsm_lsuop;
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wire dcfsm_read;
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wire dcfsm_write;
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wire dc_en;
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wire [1:0] mem2reg_addr;
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reg hit;
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reg hit;
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reg [1:0] valid_div;
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reg [1:0] valid_div;
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reg [3:0] dcbiu_sel;
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reg [1:0] bypass_wait;
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wire queue;
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wire queue;
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wire cntrbusy;
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wire cntrbusy;
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wire dcbiu_valid;
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wire dcbiu_valid;
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assign dcbiu_addr = dc_addr;
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assign dcbiu_addr = dc_addr;
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assign dctag_we = refill;
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assign dctag_we = refill;
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assign dcbiu_dataout = from_dcram;
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assign dcbiu_dataout = (dc_en) ? from_dcram : lsu_datain_memaligned;
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// Bypases of DC
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assign dc_en = 1'b0;
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assign dcfsm_lsuop = (dc_en) ? dclsu_lsuop : `LSUOP_NOP;
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assign dcbiu_read = (dc_en) ? dcfsm_read : (dclsu_lsuop && ~dclsu_lsuop[3]);
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assign dcbiu_write = (dc_en) ? dcfsm_write : (dclsu_lsuop && dclsu_lsuop[3]);
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always @(dc_en or dclsu_lsuop or dclsu_addr)
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casex({dc_en, dclsu_lsuop, dclsu_addr[1:0]})
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{1'b0, `LSUOP_SB, 2'b00} : dcbiu_sel <= #1 4'b1000;
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{1'b0, `LSUOP_SB, 2'b01} : dcbiu_sel <= #1 4'b0100;
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{1'b0, `LSUOP_SB, 2'b10} : dcbiu_sel <= #1 4'b0010;
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{1'b0, `LSUOP_SB, 2'b11} : dcbiu_sel <= #1 4'b0001;
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{1'b0, `LSUOP_SH, 2'b00} : dcbiu_sel <= #1 4'b1100;
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{1'b0, `LSUOP_SH, 2'b10} : dcbiu_sel <= #1 4'b0011;
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{1'b0, `LSUOP_SW, 2'b00} : dcbiu_sel <= #1 4'b1111;
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{1'b0, `LSUOP_LBZ, 2'b00}, {1'b0, `LSUOP_LBS, 2'b00} : dcbiu_sel <= #1 4'b1000;
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{1'b0, `LSUOP_LBZ, 2'b01}, {1'b0, `LSUOP_LBS, 2'b01} : dcbiu_sel <= #1 4'b0100;
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{1'b0, `LSUOP_LBZ, 2'b10}, {1'b0, `LSUOP_LBS, 2'b10} : dcbiu_sel <= #1 4'b0010;
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{1'b0, `LSUOP_LBZ, 2'b11}, {1'b0, `LSUOP_LBS, 2'b11} : dcbiu_sel <= #1 4'b0001;
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{1'b0, `LSUOP_LHZ, 2'b00}, {1'b0, `LSUOP_LHS, 2'b00} : dcbiu_sel <= #1 4'b1100;
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{1'b0, `LSUOP_LHZ, 2'b10}, {1'b0, `LSUOP_LHS, 2'b10} : dcbiu_sel <= #1 4'b0011;
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{1'b0, `LSUOP_LWZ, 2'b00}, {1'b0, `LSUOP_LWS, 2'b00} : dcbiu_sel <= #1 4'b1111;
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7'b1xxxxxx : dcbiu_sel <= #1 4'b1111;
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default : dcbiu_sel <= #1 4'b0000;
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endcase
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// assign dc_stall = dcbiu_read | dcbiu_write | refill_start; // can't remember if it works
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assign mem2reg_addr = (dc_en) ? saved_addr[1:0] : dclsu_addr[1:0];
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assign queue = (refill && dclsu_lsuop && !refill_first & !refill_rest) ? 1'b1 : 1'b0;
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// Wait for DC bypass acess
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always @(posedge rst or posedge clk)
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if (rst)
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bypass_wait <= #1 2'b0;
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else if (dcbiu_valid)
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bypass_wait <= #1 2'b0;
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else if (dcbiu_read | dcbiu_write)
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bypass_wait <= #1 {bypass_wait, 1'b1};
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else
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bypass_wait <= #1 2'b00;
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// assign dc_stall = dcfsm_read | dcfsm_write | refill_start; // can't remember if it works
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assign queue = (refill && dcfsm_lsuop && !refill_first & !refill_rest) ? 1'b1 : 1'b0;
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// assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue; // kind of working
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// assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue; // kind of working
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assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy;
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assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy | (~dc_en & bypass_wait[1] & ~dcbiu_valid);
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// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
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// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
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assign dc_addr = (refill == 1'b1) ? saved_addr : dclsu_addr;
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assign dc_addr = (refill == 1'b1) ? saved_addr : dclsu_addr;
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// Select between input data generated by LSU or by BIU
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// Select between input data generated by LSU or by BIU
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assign to_dcram = (refill == 1'b1) ? dcbiu_datain : lsu_datain_memaligned;
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assign to_dcram = (refill == 1'b1) ? dcbiu_datain : lsu_datain_memaligned;
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// Select between data generated by DCRAM or passed by BIU
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// Select between data generated by DCRAM or passed by BIU
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assign to_mem2reg = (refill_first == 1'b1) ? dcbiu_datain : from_dcram;
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assign to_mem2reg = (refill_first == 1'b1) | (~dc_en) ? dcbiu_datain : from_dcram;
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// Tag comparison
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// Tag comparison
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always @(tag or saved_addr) begin
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always @(tag or saved_addr) begin
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if (tag == saved_addr[31:13])
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if (tag == saved_addr[31:13])
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hit <= #1 1'b1;
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hit <= #1 1'b1;
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| Line 157... |
Line 206... |
);
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);
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dc_fsm dc_fsm(
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dc_fsm dc_fsm(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.lsu_op(dclsu_lsuop),
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.lsu_op(dcfsm_lsuop),
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.miss(~hit),
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.miss(~hit),
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.biudata_valid(dcbiu_valid),
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.biudata_valid(dcbiu_valid),
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.start_addr(dclsu_addr),
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.start_addr(dclsu_addr),
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.saved_addr(saved_addr),
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.saved_addr(saved_addr),
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.refill(refill),
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.refill(refill),
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.refill_first(refill_first),
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.refill_first(refill_first),
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.refill_prepare(refill_prepare),
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.refill_prepare(refill_prepare),
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.dcram_we(dcram_we),
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.dcram_we(dcram_we),
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.biu_read(dcbiu_read),
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.biu_read(dcfsm_read),
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.biu_write(dcbiu_write),
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.biu_write(dcfsm_write),
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.refill_rest(refill_rest),
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.refill_rest(refill_rest),
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.cntrbusy(cntrbusy)
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.cntrbusy(cntrbusy)
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);
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);
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// Regfile-to-memory aligner
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// Regfile-to-memory aligner
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Line 251... |
.tpdw(tpdw)
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.tpdw(tpdw)
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);
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);
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// Memory-to-regfile aligner
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// Memory-to-regfile aligner
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mem2reg mem2reg(
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mem2reg mem2reg(
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.addr(saved_addr[1:0]),
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.addr(mem2reg_addr[1:0]),
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.lsu_op(dclsu_lsuop),
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.lsu_op(dclsu_lsuop),
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.memdata(to_mem2reg),
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.memdata(to_mem2reg),
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.regdata(dclsu_dataout)
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.regdata(dclsu_dataout)
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);
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);
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