| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/07/22 03:31:53 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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`include "general.h"
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`include "timescale.v"
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`include "defines.v"
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//
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// Data cache
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// Data cache
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//
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module dc(
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// Rst, clk and clock control
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clk, rst, clkdiv_by_2,
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// External i/f
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dcbiu_rdy, dcbiu_datain, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dcbiu_sel,
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module dc(clk, rst, clkdiv_by_2, dcbiu_rdy, dclsu_addr, dclsu_lsuop, dclsu_datain, dcbiu_datain,
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// Inernal i/f
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dclsu_dataout, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dclsu_stall, dcbiu_sel,
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dc_en, dclsu_addr, dclsu_lsuop, dclsu_datain, dclsu_dataout, dclsu_stall,
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tp2w, tp3w, tpdw
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// Trace
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tp2w
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);
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);
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parameter dw = `OPERAND_WIDTH;
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parameter dw = `OPERAND_WIDTH;
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input clkdiv_by_2;
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input clkdiv_by_2;
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//
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// External I/F
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//
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input dcbiu_rdy;
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input dcbiu_rdy;
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input [dw-1:0] dcbiu_datain;
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output [31:0] dcbiu_addr;
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output dcbiu_read;
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output dcbiu_write;
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output [3:0] dcbiu_sel;
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//
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// Internal I/F
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//
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input dc_en;
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input [31:0] dclsu_addr;
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input [31:0] dclsu_addr;
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input [`LSUOP_WIDTH-1:0] dclsu_lsuop;
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input [`LSUOP_WIDTH-1:0] dclsu_lsuop;
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input [dw-1:0] dclsu_datain;
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input [dw-1:0] dclsu_datain;
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input [dw-1:0] dcbiu_datain;
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output [dw-1:0] dclsu_dataout;
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output [dw-1:0] dclsu_dataout;
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output [dw-1:0] dcbiu_dataout;
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output [dw-1:0] dcbiu_dataout;
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output [31:0] dcbiu_addr;
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output dcbiu_read;
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output dcbiu_write;
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output dclsu_stall;
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output dclsu_stall;
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output [3:0] dcbiu_sel;
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//
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// Trace
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//
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input [`TP2W_WIDTH-1:0] tp2w;
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input [`TP2W_WIDTH-1:0] tp2w;
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input [`TP3W_WIDTH-1:0] tp3w;
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input [31:0] tpdw;
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//
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// Internal wires and regs
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//
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wire [18:0] tag;
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wire [18:0] tag;
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wire [dw-1:0] to_dcram;
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wire [dw-1:0] to_dcram;
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wire [dw-1:0] from_dcram;
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wire [dw-1:0] from_dcram;
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wire [dw-1:0] to_mem2reg;
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wire [dw-1:0] to_mem2reg;
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wire [31:0] saved_addr;
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wire [31:0] saved_addr;
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| Line 96... |
Line 131... |
wire refill_start;
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wire refill_start;
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wire refill_rest;
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wire refill_rest;
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wire [`LSUOP_WIDTH-1:0] dcfsm_lsuop;
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wire [`LSUOP_WIDTH-1:0] dcfsm_lsuop;
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wire dcfsm_read;
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wire dcfsm_read;
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wire dcfsm_write;
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wire dcfsm_write;
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wire dc_en;
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wire [1:0] mem2reg_addr;
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wire [1:0] mem2reg_addr;
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reg hit;
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reg hit;
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reg [1:0] valid_div;
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reg [1:0] valid_div;
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reg [3:0] dcbiu_sel;
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reg [3:0] dcbiu_sel;
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reg [1:0] bypass_wait;
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reg [1:0] bypass_wait;
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wire queue;
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wire queue;
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wire cntrbusy;
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wire cntrbusy;
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wire dcbiu_valid;
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wire dcbiu_valid;
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//
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// Simple assignments
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//
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assign dcbiu_addr = dc_addr;
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assign dcbiu_addr = dc_addr;
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assign dctag_we = refill;
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assign dctag_we = refill;
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//
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// Data to BIU is from DCRAM when DC is enabled or from LSU when
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// DC is disabled
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//
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assign dcbiu_dataout = (dc_en) ? from_dcram : lsu_datain_memaligned;
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assign dcbiu_dataout = (dc_en) ? from_dcram : lsu_datain_memaligned;
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// Bypases of DC
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//
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assign dc_en = 1'b0;
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// Bypases of the DC when DC is disabled
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//
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assign dcfsm_lsuop = (dc_en) ? dclsu_lsuop : `LSUOP_NOP;
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assign dcfsm_lsuop = (dc_en) ? dclsu_lsuop : `LSUOP_NOP;
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assign dcbiu_read = (dc_en) ? dcfsm_read : (dclsu_lsuop && ~dclsu_lsuop[3]);
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assign dcbiu_read = (dc_en) ? dcfsm_read : (dclsu_lsuop && ~dclsu_lsuop[3]);
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assign dcbiu_write = (dc_en) ? dcfsm_write : (dclsu_lsuop && dclsu_lsuop[3]);
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assign dcbiu_write = (dc_en) ? dcfsm_write : (dclsu_lsuop && dclsu_lsuop[3]);
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always @(dc_en or dclsu_lsuop or dclsu_addr)
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always @(dc_en or dclsu_lsuop or dclsu_addr)
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casex({dc_en, dclsu_lsuop, dclsu_addr[1:0]})
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casex({dc_en, dclsu_lsuop, dclsu_addr[1:0]})
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| Line 139... |
Line 180... |
default : dcbiu_sel <= #1 4'b0000;
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default : dcbiu_sel <= #1 4'b0000;
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endcase
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endcase
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assign mem2reg_addr = (dc_en) ? saved_addr[1:0] : dclsu_addr[1:0];
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assign mem2reg_addr = (dc_en) ? saved_addr[1:0] : dclsu_addr[1:0];
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//
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// Wait for DC bypass acess
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// Wait for DC bypass acess
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//
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always @(posedge rst or posedge clk)
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always @(posedge rst or posedge clk)
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if (rst)
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if (rst)
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bypass_wait <= #1 2'b0;
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bypass_wait <= #1 2'b0;
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else if (dcbiu_valid)
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else if (dcbiu_valid)
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bypass_wait <= #1 2'b0;
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bypass_wait <= #1 2'b0;
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else if (dcbiu_read | dcbiu_write)
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else if (dcbiu_read | dcbiu_write)
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bypass_wait <= #1 {bypass_wait, 1'b1};
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bypass_wait <= #1 {bypass_wait, 1'b1};
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else
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else
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bypass_wait <= #1 2'b00;
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bypass_wait <= #1 2'b00;
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// assign dc_stall = dcfsm_read | dcfsm_write | refill_start; // can't remember if it works
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//
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// Queue
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//
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assign queue = (refill && dcfsm_lsuop && !refill_first & !refill_rest) ? 1'b1 : 1'b0;
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assign queue = (refill && dcfsm_lsuop && !refill_first & !refill_rest) ? 1'b1 : 1'b0;
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// assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue; // kind of working
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//
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// DC/LSU stall
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//
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assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy | (~dc_en & bypass_wait[1] & ~dcbiu_valid);
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assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy | (~dc_en & bypass_wait[1] & ~dcbiu_valid);
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//
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// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
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// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
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//
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assign dc_addr = (refill == 1'b1) ? saved_addr : dclsu_addr;
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assign dc_addr = (refill == 1'b1) ? saved_addr : dclsu_addr;
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//
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// Select between input data generated by LSU or by BIU
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// Select between input data generated by LSU or by BIU
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//
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assign to_dcram = (refill == 1'b1) ? dcbiu_datain : lsu_datain_memaligned;
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assign to_dcram = (refill == 1'b1) ? dcbiu_datain : lsu_datain_memaligned;
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//
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// Select between data generated by DCRAM or passed by BIU
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// Select between data generated by DCRAM or passed by BIU
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//
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assign to_mem2reg = (refill_first == 1'b1) | (~dc_en) ? dcbiu_datain : from_dcram;
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assign to_mem2reg = (refill_first == 1'b1) | (~dc_en) ? dcbiu_datain : from_dcram;
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//
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// Tag comparison
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// Tag comparison
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//
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always @(tag or saved_addr) begin
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always @(tag or saved_addr) begin
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if (tag == saved_addr[31:13])
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if (tag == saved_addr[31:13])
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hit <= #1 1'b1;
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hit <= #1 1'b1;
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else
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else
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hit <= #1 1'b0;
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hit <= #1 1'b0;
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end
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end
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//
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// Valid_div counts RISC clock cycles by modulo 4
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// Valid_div counts RISC clock cycles by modulo 4
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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valid_div <= #1 2'b0;
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valid_div <= #1 2'b0;
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else
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else
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valid_div <= #1 valid_div + 'd1;
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valid_div <= #1 valid_div + 'd1;
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//
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// dcbiu_valid is one RISC clock cycle long dcbiu_rdy.
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// dcbiu_valid is one RISC clock cycle long dcbiu_rdy.
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// dcbiu_rdy is two or four RISC clock cycles long because memory
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// dcbiu_rdy is two or four RISC clock cycles long because memory
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// controller works at 1/2 or 1/4 of RISC clock freq (at 1/2 if
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// controller works at 1/2 or 1/4 of RISC clock freq (at 1/2 if
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// clkdiv_by_2 is asserted).
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// clkdiv_by_2 is asserted).
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//
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assign dcbiu_valid = dcbiu_rdy & (valid_div[1] | clkdiv_by_2) & valid_div[0];
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assign dcbiu_valid = dcbiu_rdy & (valid_div[1] | clkdiv_by_2) & valid_div[0];
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//
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// Generate refill_start that signals to frz_logic a cache linefill is about to begin
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// Generate refill_start that signals to frz_logic a cache linefill is about to begin
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//
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assign refill_start = (refill_prepare & ~hit) ? 1'b1 : 1'b0;
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assign refill_start = (refill_prepare & ~hit) ? 1'b1 : 1'b0;
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dtlb dtlb(
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//
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.clk(clk),
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// Instantiation of DC Finite State Machine
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.rst(rst),
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//
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.we(1'b0),
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.tlb_en(1'b1),
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.datain(dclsu_datain),
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.vaddr(saved_addr),
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.paddr(),
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.cache_en(),
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.tlb_miss(),
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.tp3w(tp3w),
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.tpdw(tpdw)
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);
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dc_fsm dc_fsm(
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dc_fsm dc_fsm(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.lsu_op(dcfsm_lsuop),
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.lsu_op(dcfsm_lsuop),
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.miss(~hit),
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.miss(~hit),
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| Line 221... |
Line 271... |
.biu_write(dcfsm_write),
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.biu_write(dcfsm_write),
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.refill_rest(refill_rest),
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.refill_rest(refill_rest),
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.cntrbusy(cntrbusy)
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.cntrbusy(cntrbusy)
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);
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);
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// Regfile-to-memory aligner
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//
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// Instantiation of Regfile-to-memory aligner
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//
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reg2mem reg2mem(
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reg2mem reg2mem(
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.addr(dc_addr[1:0]),
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.addr(dc_addr[1:0]),
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.lsu_op(dclsu_lsuop),
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.lsu_op(dclsu_lsuop),
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.regdata(dclsu_datain),
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.regdata(dclsu_datain),
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.memdata(lsu_datain_memaligned)
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.memdata(lsu_datain_memaligned)
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);
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);
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//
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// Instantiation of DC main memory
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//
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dc_ram dc_ram(
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dc_ram dc_ram(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.addr(dc_addr[12:2]),
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.addr(dc_addr[12:2]),
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.we(dcram_we),
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.we(dcram_we),
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.datain(to_dcram),
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.datain(to_dcram),
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.dataout(from_dcram),
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.dataout(from_dcram)
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.tp2w(tp2w),
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.tpdw(tpdw)
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);
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);
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//
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// Instantiation of DC TAG memory
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//
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dc_tag dc_tag(
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dc_tag dc_tag(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.addr(dc_addr[12:4]),
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.addr(dc_addr[12:4]),
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.we(dctag_we),
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.we(dctag_we),
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.datain(dc_addr[31:13]),
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.datain(dc_addr[31:13]),
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.dataout(tag),
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.dataout(tag)
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.tp2w(tp2w),
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.tpdw(tpdw)
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);
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);
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// Memory-to-regfile aligner
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//
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// Instatiation of Memory-to-regfile aligner
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//
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mem2reg mem2reg(
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mem2reg mem2reg(
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.addr(mem2reg_addr[1:0]),
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.addr(mem2reg_addr[1:0]),
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.lsu_op(dclsu_lsuop),
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.lsu_op(dclsu_lsuop),
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.memdata(to_mem2reg),
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.memdata(to_mem2reg),
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.regdata(dclsu_dataout)
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.regdata(dclsu_dataout)
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