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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [dc.v] - Diff between revs 168 and 170

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Rev 168	Rev 170
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2001/08/09 13:39:33 lampret`
	`// Major clean-up.`
	`//`
`// Revision 1.2 2001/07/22 03:31:53 lampret`	`// Revision 1.2 2001/07/22 03:31:53 lampret`
`// Fixed RAM's oen bug. Cache bypass under development.`	`// Fixed RAM's oen bug. Cache bypass under development.`
`//`	`//`
`// Revision 1.1 2001/07/20 00:46:03 lampret`	`// Revision 1.1 2001/07/20 00:46:03 lampret`
`// Development version of RTL. Libraries are missing.`	`// Development version of RTL. Libraries are missing.`
Line 64...	Line 67...
`clk, rst, clkdiv_by_2,`	`clk, rst, clkdiv_by_2,`

`// External i/f`	`// External i/f`
`dcbiu_rdy, dcbiu_datain, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dcbiu_sel,`	`dcbiu_rdy, dcbiu_datain, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dcbiu_sel,`

`// Inernal i/f`	`// Internal i/f`
`dc_en, dclsu_addr, dclsu_lsuop, dclsu_datain, dclsu_dataout, dclsu_stall,`	`dc_en, dclsu_addr, dclsu_lsuop, dclsu_datain, dclsu_dataout, dclsu_stall,`

`// Trace`	`// Trace`
`tp2w`	`tp2w`
`);`	`);`
Line 94...	Line 97...
`output [31:0] dcbiu_addr;`	`output [31:0] dcbiu_addr;`
`output dcbiu_read;`	`output dcbiu_read;`
`output dcbiu_write;`	`output dcbiu_write;`
`output [3:0] dcbiu_sel;`	`output [3:0] dcbiu_sel;`


`//`	`//`
`// Internal I/F`	`// Internal I/F`
`//`	`//`
`input dc_en;`	`input dc_en;`
`input [31:0] dclsu_addr;`	`input [31:0] dclsu_addr;`
Line 181...	Line 183...
`endcase`	`endcase`

`assign mem2reg_addr = (dc_en) ? saved_addr[1:0] : dclsu_addr[1:0];`	`assign mem2reg_addr = (dc_en) ? saved_addr[1:0] : dclsu_addr[1:0];`

`//`	`//`
`// Wait for DC bypass acess`	`// Wait for DC bypass access`
`//`	`//`
`always @(posedge rst or posedge clk)`	`always @(posedge rst or posedge clk)`
`if (rst)`	`if (rst)`
`bypass_wait <= #1 2'b0;`	`bypass_wait <= #1 2'b0;`
`else if (dcbiu_valid)`	`else if (dcbiu_valid)`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [dc.v] - Diff between revs 168 and 170