| Line 76... |
Line 76... |
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// Internal i/f
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// Internal i/f
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dc_en, dclsu_addr, dclsu_lsuop, dclsu_datain, dclsu_dataout, dclsu_stall, dclsu_unstall,
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dc_en, dclsu_addr, dclsu_lsuop, dclsu_datain, dclsu_dataout, dclsu_stall, dclsu_unstall,
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// SPRs
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// SPRs
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spr_cs, spr_write, spr_addr, spr_dat_i,
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spr_cs, spr_write, spr_addr, spr_dat_i
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// Trace
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tp2w
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);
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);
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parameter dw = `OPERAND_WIDTH;
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parameter dw = `OPERAND_WIDTH;
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//
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//
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| Line 126... |
Line 123... |
input spr_write;
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input spr_write;
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input [31:0] spr_addr;
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input [31:0] spr_addr;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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//
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//
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// Trace
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//
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input [`TP2W_WIDTH-1:0] tp2w;
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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wire tag_v;
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wire tag_v;
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wire [18:0] tag;
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wire [18:0] tag;
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wire [dw-1:0] to_dcram;
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wire [dw-1:0] to_dcram;
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| Line 185... |
Line 177... |
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//
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//
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// Bypases of the DC when DC is disabled
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// Bypases of the DC when DC is disabled
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//
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//
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assign dcfsm_lsuop = (dc_en) ? dclsu_lsuop : `LSUOP_NOP;
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assign dcfsm_lsuop = (dc_en) ? dclsu_lsuop : `LSUOP_NOP;
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assign dcbiu_read = (dc_en) ? dcfsm_read : (dclsu_lsuop && ~dclsu_lsuop[3]);
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assign dcbiu_read = (dc_en) ? dcfsm_read : ((|dclsu_lsuop) && ~dclsu_lsuop[3]);
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assign dcbiu_write = (dc_en) ? dcfsm_write : (dclsu_lsuop && dclsu_lsuop[3]);
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assign dcbiu_write = (dc_en) ? dcfsm_write : ((|dclsu_lsuop) && dclsu_lsuop[3]);
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always @(dc_en or dclsu_lsuop or dclsu_addr)
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always @(dc_en or dclsu_lsuop or dclsu_addr)
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casex({dc_en, dclsu_lsuop, dclsu_addr[1:0]})
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casex({dc_en, dclsu_lsuop, dclsu_addr[1:0]})
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{1'b0, `LSUOP_SB, 2'b00} : dcbiu_sel <= #1 4'b1000;
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{1'b0, `LSUOP_SB, 2'b00} : dcbiu_sel = 4'b1000;
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{1'b0, `LSUOP_SB, 2'b01} : dcbiu_sel <= #1 4'b0100;
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{1'b0, `LSUOP_SB, 2'b01} : dcbiu_sel = 4'b0100;
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{1'b0, `LSUOP_SB, 2'b10} : dcbiu_sel <= #1 4'b0010;
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{1'b0, `LSUOP_SB, 2'b10} : dcbiu_sel = 4'b0010;
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{1'b0, `LSUOP_SB, 2'b11} : dcbiu_sel <= #1 4'b0001;
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{1'b0, `LSUOP_SB, 2'b11} : dcbiu_sel = 4'b0001;
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{1'b0, `LSUOP_SH, 2'b00} : dcbiu_sel <= #1 4'b1100;
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{1'b0, `LSUOP_SH, 2'b00} : dcbiu_sel = 4'b1100;
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{1'b0, `LSUOP_SH, 2'b10} : dcbiu_sel <= #1 4'b0011;
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{1'b0, `LSUOP_SH, 2'b10} : dcbiu_sel = 4'b0011;
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{1'b0, `LSUOP_SW, 2'b00} : dcbiu_sel <= #1 4'b1111;
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{1'b0, `LSUOP_SW, 2'b00} : dcbiu_sel = 4'b1111;
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{1'b0, `LSUOP_LBZ, 2'b00}, {1'b0, `LSUOP_LBS, 2'b00} : dcbiu_sel <= #1 4'b1000;
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{1'b0, `LSUOP_LBZ, 2'b00}, {1'b0, `LSUOP_LBS, 2'b00} : dcbiu_sel = 4'b1000;
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{1'b0, `LSUOP_LBZ, 2'b01}, {1'b0, `LSUOP_LBS, 2'b01} : dcbiu_sel <= #1 4'b0100;
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{1'b0, `LSUOP_LBZ, 2'b01}, {1'b0, `LSUOP_LBS, 2'b01} : dcbiu_sel = 4'b0100;
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{1'b0, `LSUOP_LBZ, 2'b10}, {1'b0, `LSUOP_LBS, 2'b10} : dcbiu_sel <= #1 4'b0010;
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{1'b0, `LSUOP_LBZ, 2'b10}, {1'b0, `LSUOP_LBS, 2'b10} : dcbiu_sel = 4'b0010;
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{1'b0, `LSUOP_LBZ, 2'b11}, {1'b0, `LSUOP_LBS, 2'b11} : dcbiu_sel <= #1 4'b0001;
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{1'b0, `LSUOP_LBZ, 2'b11}, {1'b0, `LSUOP_LBS, 2'b11} : dcbiu_sel = 4'b0001;
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{1'b0, `LSUOP_LHZ, 2'b00}, {1'b0, `LSUOP_LHS, 2'b00} : dcbiu_sel <= #1 4'b1100;
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{1'b0, `LSUOP_LHZ, 2'b00}, {1'b0, `LSUOP_LHS, 2'b00} : dcbiu_sel = 4'b1100;
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{1'b0, `LSUOP_LHZ, 2'b10}, {1'b0, `LSUOP_LHS, 2'b10} : dcbiu_sel <= #1 4'b0011;
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{1'b0, `LSUOP_LHZ, 2'b10}, {1'b0, `LSUOP_LHS, 2'b10} : dcbiu_sel = 4'b0011;
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{1'b0, `LSUOP_LWZ, 2'b00}, {1'b0, `LSUOP_LWS, 2'b00} : dcbiu_sel <= #1 4'b1111;
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{1'b0, `LSUOP_LWZ, 2'b00}, {1'b0, `LSUOP_LWS, 2'b00} : dcbiu_sel = 4'b1111;
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7'b1xxxxxx : dcbiu_sel <= #1 4'b1111;
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7'b1xxxxxx : dcbiu_sel = 4'b1111;
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default : dcbiu_sel <= #1 4'b0000;
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default : dcbiu_sel = 4'b0000;
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endcase
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endcase
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assign mem2reg_addr = (dc_en) ? saved_addr[1:0] : dclsu_addr[1:0];
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assign mem2reg_addr = (dc_en) ? saved_addr[1:0] : dclsu_addr[1:0];
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//
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//
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// Wait for DC bypass access
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// Wait for DC bypass access
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//
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//
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always @(posedge rst or posedge clk)
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always @(posedge rst or posedge clk)
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if (rst)
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if (rst)
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bypass_wait <= #1 2'b0;
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bypass_wait <= #1 2'b00;
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else if (dcbiu_valid)
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else if (dcbiu_valid)
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bypass_wait <= #1 2'b0;
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bypass_wait <= #1 2'b00;
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else if (dcbiu_read | dcbiu_write)
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else if (dcbiu_read | dcbiu_write)
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bypass_wait <= #1 {bypass_wait, 1'b1};
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bypass_wait <= #1 {bypass_wait[0], 1'b1};
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else
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else
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bypass_wait <= #1 2'b00;
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bypass_wait <= #1 2'b00;
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//
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//
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// Queue
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// Queue
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//
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//
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assign queue = (refill && dcfsm_lsuop && !refill_first & !refill_rest) ? 1'b1 : 1'b0;
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assign queue = (refill && (|dcfsm_lsuop) && !refill_first && !refill_rest) ? 1'b1 : 1'b0;
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//
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//
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// DC/LSU stall
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// DC/LSU stall
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//
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//
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//assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy | (~dc_en & bypass_wait[1] & ~dcbiu_valid);
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//assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy | (~dc_en & bypass_wait[1] & ~dcbiu_valid);
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| Line 253... |
Line 245... |
//
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//
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// Tag comparison
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// Tag comparison
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//
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//
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always @(tag or saved_addr) begin
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always @(tag or saved_addr) begin
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if ((tag == saved_addr[31:13]) && tag_v)
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if ((tag == saved_addr[31:13]) && tag_v)
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hit <= #1 1'b1;
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hit = 1'b1;
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else
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else
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hit <= #1 1'b0;
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hit = 1'b0;
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end
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end
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//
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//
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// Valid_div counts RISC clock cycles by modulo 4
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// Valid_div counts RISC clock cycles by modulo 4
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//
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//
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