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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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`include "general.h"
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`include "timescale.v"
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`include "defines.v"
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`define DCFSM_IDLE 'd0
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`define DCFSM_IDLE 'd0
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`define DCFSM_DOLOAD 'd1
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`define DCFSM_DOLOAD 'd1
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`define DCFSM_LREFILL3 'd2
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`define DCFSM_LREFILL3 'd2
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`define DCFSM_DOSTORE 'd3
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`define DCFSM_DOSTORE 'd3
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`define DCFSM_SREFILL3 'd4
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`define DCFSM_SREFILL3 'd4
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`define DCFSM_SMEMWR 'd5
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`define DCFSM_SMEMWR 'd5
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//
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// Data cache FSM for cache line of 16 bytes (4x singleword)
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// Data cache FSM for cache line of 16 bytes (4x singleword)
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//
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module dc_fsm(clk, rst, lsu_op, miss, biudata_valid, start_addr, saved_addr, refill, refill_first, refill_prepare, dcram_we, biu_read, biu_write, refill_rest, cntrbusy);
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module dc_fsm(
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// Clock and reset
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clk, rst,
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// Internal i/f to top level DC
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lsu_op, miss, biudata_valid, start_addr, saved_addr,
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refill, refill_first, refill_prepare, dcram_we,
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biu_read, biu_write, refill_rest, cntrbusy
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);
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//
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// I/O
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input miss;
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input miss;
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input biudata_valid;
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input biudata_valid;
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input [31:0] start_addr;
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input [31:0] start_addr;
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output biu_read;
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output biu_read;
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output biu_write;
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output biu_write;
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output refill_rest;
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output refill_rest;
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output cntrbusy;
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output cntrbusy;
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//
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// Internal wires and regs
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//
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wire dcache_off = 1'b0;
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wire dcache_off = 1'b0;
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reg [31:0] saved_addr;
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reg [31:0] saved_addr;
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reg refill;
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reg refill;
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reg [3:0] dcram_we;
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reg [3:0] dcram_we;
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reg [2:0] state;
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reg [2:0] state;
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reg [2:0] cnt;
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reg [2:0] cnt;
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reg refill_first;
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reg refill_first;
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reg refill_prepare;
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reg refill_prepare;
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reg biu_read;
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reg biu_read;
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reg biu_write;
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reg biu_write;
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reg refill_rest;
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reg refill_rest;
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reg cntrbusy;
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reg cntrbusy;
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//
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// Generation of DCRAM write enable
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//
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always @(refill_first or refill or biudata_valid or lsu_op or start_addr or biu_write) begin
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always @(refill_first or refill or biudata_valid or lsu_op or start_addr or biu_write) begin
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if (refill_first || !refill)
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if (refill_first || !refill)
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casex({lsu_op, start_addr[1:0]})
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casex({lsu_op, start_addr[1:0]})
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{`LSUOP_SB, 2'b00} : dcram_we <= #1 4'b1000 ^ {4{refill_first}};
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{`LSUOP_SB, 2'b00} : dcram_we <= #1 4'b1000 ^ {4{refill_first}};
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{`LSUOP_SB, 2'b01} : dcram_we <= #1 4'b0100 ^ {4{refill_first}};
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{`LSUOP_SB, 2'b01} : dcram_we <= #1 4'b0100 ^ {4{refill_first}};
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endcase
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endcase
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else
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else
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dcram_we <= #1 {4{refill & biudata_valid & ~biu_write}};
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dcram_we <= #1 {4{refill & biudata_valid & ~biu_write}};
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end
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end
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//
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// Main DC FSM
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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refill <= #1 1'b0;
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refill <= #1 1'b0;
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state <= #1 3`DCFSM_IDLE;
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state <= #1 3`DCFSM_IDLE;
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biu_read <= #1 1'b0;
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biu_read <= #1 1'b0;
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