| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.2 2001/08/09 13:39:33 lampret
|
|
// Major clean-up.
|
|
//
|
// Revision 1.1 2001/07/20 00:46:03 lampret
|
// Revision 1.1 2001/07/20 00:46:03 lampret
|
// Development version of RTL. Libraries are missing.
|
// Development version of RTL. Libraries are missing.
|
//
|
//
|
//
|
//
|
|
|
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
|
// synopsys translate_on
|
`include "defines.v"
|
`include "defines.v"
|
|
|
`define DCFSM_IDLE 'd0
|
`define DCFSM_IDLE 3'd0
|
`define DCFSM_DOLOAD 'd1
|
`define DCFSM_DOLOAD 3'd1
|
`define DCFSM_LREFILL3 'd2
|
`define DCFSM_LREFILL3 3'd2
|
`define DCFSM_DOSTORE 'd3
|
`define DCFSM_DOSTORE 3'd3
|
`define DCFSM_SREFILL3 'd4
|
`define DCFSM_SREFILL3 3'd4
|
`define DCFSM_SMEMWR 'd5
|
`define DCFSM_SMEMWR 3'd5
|
|
|
//
|
//
|
// Data cache FSM for cache line of 16 bytes (4x singleword)
|
// Data cache FSM for cache line of 16 bytes (4x singleword)
|
//
|
//
|
|
|
| Line 133... |
Line 138... |
// Main DC FSM
|
// Main DC FSM
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
refill <= #1 1'b0;
|
refill <= #1 1'b0;
|
state <= #1 3`DCFSM_IDLE;
|
state <= #1 `DCFSM_IDLE;
|
biu_read <= #1 1'b0;
|
biu_read <= #1 1'b0;
|
biu_write <= #1 1'b0;
|
biu_write <= #1 1'b0;
|
saved_addr <= #1 32'b0;
|
saved_addr <= #1 32'b0;
|
refill_prepare <= #1 1'b0;
|
refill_prepare <= #1 1'b0;
|
refill_rest <= #1 1'b0;
|
refill_rest <= #1 1'b0;
|
| Line 146... |
Line 151... |
else
|
else
|
case (state) // synopsys full_case parallel_case
|
case (state) // synopsys full_case parallel_case
|
`DCFSM_IDLE :
|
`DCFSM_IDLE :
|
casex(lsu_op)
|
casex(lsu_op)
|
`LSUOP_LBZ, `LSUOP_LBS, `LSUOP_LHZ, `LSUOP_LHS, `LSUOP_LWZ: begin
|
`LSUOP_LBZ, `LSUOP_LBS, `LSUOP_LHZ, `LSUOP_LHS, `LSUOP_LWZ: begin
|
|
`ifdef OR1200_VERBOSE
|
|
// synopsys translate_off
|
$display("%t: DC_FSM Load op %h start_addr %h", $time, lsu_op, start_addr);
|
$display("%t: DC_FSM Load op %h start_addr %h", $time, lsu_op, start_addr);
|
state <= #1 3`DCFSM_DOLOAD;
|
// synopsys translate_on
|
|
`endif
|
|
state <= #1 `DCFSM_DOLOAD;
|
refill <= #1 1'b0;
|
refill <= #1 1'b0;
|
saved_addr <= #1 start_addr;
|
saved_addr <= #1 start_addr;
|
refill_first <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
refill_prepare <= #1 1'b1;
|
refill_prepare <= #1 1'b1;
|
biu_read <= #1 1'b0;
|
biu_read <= #1 1'b0;
|
biu_write <= #1 1'b0;
|
biu_write <= #1 1'b0;
|
refill_rest <= #1 1'b0;
|
refill_rest <= #1 1'b0;
|
cntrbusy <= #1 1'b0;
|
cntrbusy <= #1 1'b0;
|
end
|
end
|
`LSUOP_SB, `LSUOP_SH, `LSUOP_SW: begin
|
`LSUOP_SB, `LSUOP_SH, `LSUOP_SW: begin
|
|
`ifdef OR1200_VERBOSE
|
|
// synopsys translate_off
|
$display("%t: DC_FSM Store op %h start_addr %h", $time, lsu_op, start_addr);
|
$display("%t: DC_FSM Store op %h start_addr %h", $time, lsu_op, start_addr);
|
state <= #1 3`DCFSM_DOSTORE;
|
// synopsys translate_on
|
|
`endif
|
|
state <= #1 `DCFSM_DOSTORE;
|
refill <= #1 1'b0;
|
refill <= #1 1'b0;
|
saved_addr <= #1 start_addr;
|
saved_addr <= #1 start_addr;
|
refill_first <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
refill_prepare <= #1 1'b1;
|
refill_prepare <= #1 1'b1;
|
biu_read <= #1 1'b0;
|
biu_read <= #1 1'b0;
|
biu_write <= #1 1'b0;
|
biu_write <= #1 1'b0;
|
refill_rest <= #1 1'b0;
|
refill_rest <= #1 1'b0;
|
cntrbusy <= #1 1'b0;
|
cntrbusy <= #1 1'b0;
|
end
|
end
|
default: begin
|
default: begin
|
state <= #1 3`DCFSM_IDLE;
|
state <= #1 `DCFSM_IDLE;
|
refill <= #1 1'b0;
|
refill <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
refill_prepare <= #1 1'b0;
|
refill_prepare <= #1 1'b0;
|
refill_rest <= #1 1'b0;
|
refill_rest <= #1 1'b0;
|
biu_read <= #1 1'b0;
|
biu_read <= #1 1'b0;
|
| Line 182... |
Line 195... |
cntrbusy <= #1 1'b0;
|
cntrbusy <= #1 1'b0;
|
end
|
end
|
endcase
|
endcase
|
`DCFSM_DOLOAD:
|
`DCFSM_DOLOAD:
|
if (dcache_off) begin
|
if (dcache_off) begin
|
// $display("%t: DC_FSM DCache off", $time);
|
`ifdef OR1200_VERBOSE
|
state <= #1 3`DCFSM_DOLOAD;
|
// synopsys translate_off
|
|
$display("%t: DC_FSM DCache off", $time);
|
|
// synopsys translate_on
|
|
`endif
|
|
state <= #1 `DCFSM_DOLOAD;
|
refill <= #1 1'b1;
|
refill <= #1 1'b1;
|
refill_first <= #1 1'b1;
|
refill_first <= #1 1'b1;
|
refill_prepare <= #1 1'b0;
|
refill_prepare <= #1 1'b0;
|
refill_rest <= #1 1'b0;
|
refill_rest <= #1 1'b0;
|
biu_read <= #1 1'b1;
|
biu_read <= #1 1'b1;
|
if (biudata_valid) begin
|
if (biudata_valid) begin
|
state <= #1 3`DCFSM_IDLE;
|
state <= #1 `DCFSM_IDLE;
|
refill <= #1 1'b0;
|
refill <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
biu_read <= #1 1'b0;
|
biu_read <= #1 1'b0;
|
saved_addr <= #1 start_addr;
|
saved_addr <= #1 start_addr;
|
end
|
end
|
end else
|
end else
|
if (miss) begin
|
if (miss) begin
|
|
`ifdef OR1200_VERBOSE
|
|
// synopsys translate_off
|
$display("%t: DC_FSM Load miss", $time);
|
$display("%t: DC_FSM Load miss", $time);
|
state <= #1 3`DCFSM_LREFILL3;
|
// synopsys translate_on
|
|
`endif
|
|
state <= #1 `DCFSM_LREFILL3;
|
refill <= #1 1'b1;
|
refill <= #1 1'b1;
|
refill_first <= #1 1'b1;
|
refill_first <= #1 1'b1;
|
refill_prepare <= #1 1'b0;
|
refill_prepare <= #1 1'b0;
|
cnt <= #1 3'd3;
|
cnt <= #1 3'd3;
|
biu_read <= #1 1'b1;
|
biu_read <= #1 1'b1;
|
end
|
end
|
else begin
|
else begin
|
|
`ifdef OR1200_VERBOSE
|
|
// synopsys translate_off
|
$display("%t: DC_FSM Load hit", $time);
|
$display("%t: DC_FSM Load hit", $time);
|
state <= #1 3`DCFSM_IDLE;
|
// synopsys translate_on
|
|
`endif
|
|
state <= #1 `DCFSM_IDLE;
|
refill <= #1 1'b0;
|
refill <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
refill_prepare <= #1 1'b0;
|
refill_prepare <= #1 1'b0;
|
cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
|
cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
|
end
|
end
|
`DCFSM_LREFILL3 : begin
|
`DCFSM_LREFILL3 : begin
|
if (biudata_valid && cnt) begin
|
if (biudata_valid && cnt) begin
|
|
`ifdef OR1200_VERBOSE
|
|
// synopsys translate_off
|
$display("%t: DC_FSM Load refill %d", $time, cnt);
|
$display("%t: DC_FSM Load refill %d", $time, cnt);
|
|
// synopsys translate_on
|
|
`endif
|
cnt <= #1 cnt - 'd1;
|
cnt <= #1 cnt - 'd1;
|
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
|
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
|
refill_first <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
end
|
end
|
else if (biudata_valid) begin
|
else if (biudata_valid) begin
|
|
`ifdef OR1200_VERBOSE
|
|
// synopsys translate_off
|
$display("%t: DC_FSM Load refill end", $time, cnt);
|
$display("%t: DC_FSM Load refill end", $time, cnt);
|
state <= #1 3`DCFSM_IDLE;
|
// synopsys translate_on
|
|
`endif
|
|
state <= #1 `DCFSM_IDLE;
|
refill <= #1 1'b0;
|
refill <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
biu_read <= #1 1'b0;
|
biu_read <= #1 1'b0;
|
cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
|
cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
|
end
|
end
|
refill_rest <= #1 ~refill_first & refill;
|
refill_rest <= #1 ~refill_first & refill;
|
end
|
end
|
`DCFSM_DOSTORE:
|
`DCFSM_DOSTORE:
|
if (miss) begin
|
if (miss) begin
|
|
`ifdef OR1200_VERBOSE
|
|
// synopsys translate_off
|
$display("%t: DC_FSM Store miss", $time);
|
$display("%t: DC_FSM Store miss", $time);
|
state <= #1 3`DCFSM_SREFILL3;
|
// synopsys translate_on
|
|
`endif
|
|
state <= #1 `DCFSM_SREFILL3;
|
refill <= #1 1'b1;
|
refill <= #1 1'b1;
|
refill_first <= #1 1'b1;
|
refill_first <= #1 1'b1;
|
refill_prepare <= #1 1'b0;
|
refill_prepare <= #1 1'b0;
|
cnt <= #1 3'd3;
|
cnt <= #1 3'd3;
|
biu_read <= #1 1'b1;
|
biu_read <= #1 1'b1;
|
end
|
end
|
else begin
|
else begin
|
|
`ifdef OR1200_VERBOSE
|
|
// synopsys translate_off
|
$display("%t: DC_FSM Store hit", $time);
|
$display("%t: DC_FSM Store hit", $time);
|
state <= #1 3`DCFSM_SMEMWR;
|
// synopsys translate_on
|
|
`endif
|
|
state <= #1 `DCFSM_SMEMWR;
|
refill <= #1 1'b1;
|
refill <= #1 1'b1;
|
refill_first <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
refill_prepare <= #1 1'b0;
|
refill_prepare <= #1 1'b0;
|
biu_write <= #1 1'b1;
|
biu_write <= #1 1'b1;
|
biu_read <= #1 1'b0;
|
biu_read <= #1 1'b0;
|
end
|
end
|
`DCFSM_SREFILL3 : begin
|
`DCFSM_SREFILL3 : begin
|
if (biudata_valid && cnt) begin
|
if (biudata_valid && cnt) begin
|
|
`ifdef OR1200_VERBOSE
|
|
// synopsys translate_off
|
$display("%t: DC_FSM Store refill %d", $time, cnt);
|
$display("%t: DC_FSM Store refill %d", $time, cnt);
|
|
// synopsys translate_on
|
|
`endif
|
cnt <= #1 cnt - 'd1;
|
cnt <= #1 cnt - 'd1;
|
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
|
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
|
refill_first <= #1 1'b0;
|
refill_first <= #1 1'b0;
|
end
|
end
|
else if (biudata_valid) begin
|
else if (biudata_valid) begin
|
|
`ifdef OR1200_VERBOSE
|
|
// synopsys translate_off
|
$display("%t: DC_FSM Store refill almost done", $time);
|
$display("%t: DC_FSM Store refill almost done", $time);
|
state <= #1 3`DCFSM_SMEMWR;
|
// synopsys translate_on
|
|
`endif
|
|
state <= #1 `DCFSM_SMEMWR;
|
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
|
saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
|
biu_write <= #1 1'b1;
|
biu_write <= #1 1'b1;
|
biu_read <= #1 1'b0;
|
biu_read <= #1 1'b0;
|
end
|
end
|
refill_rest <= #1 ~refill_first & refill;
|
refill_rest <= #1 ~refill_first & refill;
|
end
|
end
|
`DCFSM_SMEMWR :
|
`DCFSM_SMEMWR :
|
if (biudata_valid) begin
|
if (biudata_valid) begin
|
|
`ifdef OR1200_VERBOSE
|
|
// synopsys translate_off
|
$display("%t: DC_FSM Store refill end (just finished store to external mem)", $time);
|
$display("%t: DC_FSM Store refill end (just finished store to external mem)", $time);
|
state <= #1 3`DCFSM_IDLE;
|
// synopsys translate_on
|
|
`endif
|
|
state <= #1 `DCFSM_IDLE;
|
refill <= #1 1'b0;
|
refill <= #1 1'b0;
|
biu_write <= #1 1'b0;
|
biu_write <= #1 1'b0;
|
cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
|
cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
|
end
|
end
|
endcase
|
endcase
|
