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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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`include "general.h"
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`include "timescale.v"
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`include "defines.v"
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`define NO_UTI
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`define NO_UTI
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module dc_tag(clk, addr, we, datain, dataout, tp2w, tpdw);
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module dc_tag(
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// Clock and reset
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clk, rst,
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// Internal i/f
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addr, we, datain, dataout
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);
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parameter dw = 19;
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parameter dw = 19;
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parameter aw = 9;
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parameter aw = 9;
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input [dw-1:0] datain;
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//
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output [dw-1:0] dataout;
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// I/O
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//
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input clk;
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input rst;
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input [aw-1:0] addr;
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input [aw-1:0] addr;
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input we;
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input we;
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input [dw-1:0] datain;
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output [dw-1:0] dataout;
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input clk;
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//
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// Instantiation of TAG RAM block
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input [`TP2W_WIDTH-1:0] tp2w;
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//
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input [31:0] tpdw;
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generic_spram_512x19 dc_tag0(
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wire high, low;
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assign high = 1;
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assign low = 0;
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`ifdef NO_UTI
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art_hssp_512x19 dc_tag0(
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.q(dataout),
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.clk(clk),
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.cen(low),
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.oen(low),
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.wen(~we),
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.a(addr),
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.d(datain)
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);
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`else
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art_hssp_512x19 dc_tag0(
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.q(dataout),
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.censq(),
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.oensq(),
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.wensq(),
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.asq(),
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.tq(),
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.clk(clk),
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.clk(clk),
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.cen(low),
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.rst(rst),
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.oen(low),
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.ce(1'b1),
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.wen(~we),
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.we(we),
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.a(addr),
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.oe(1'b1),
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.d(datain),
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.addr(addr),
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.tis(tp2w[`TP2W_DCT_TIS]),
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.di(datain),
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.tms(tp2w[`TP2W_DCT_TMS]),
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.do(dataout)
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.tcen(tp2w[`TP2W_DCT_TCEN]), //normally high
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.toen(tp2w[`TP2W_DCT_TOEN]),
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.tqoen(tp2w[`TP2W_DCT_TQOEN]),
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.twen(tp2w[`TP2W_DCT_TWEN]),
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.ta(tp2w[`TP2W_DCT_TA]),
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.td(tpdw[dw-1:0])
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);
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);
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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