| Line 56... |
Line 56... |
//
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//
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module du(
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module du(
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// RISC Internal Interface
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// RISC Internal Interface
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clk, rst,
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clk, rst,
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dclsu_lsuop, icfetch_op, ex_freeze, branch_op,
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du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
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du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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dclsu_lsuop, icfetch_op,
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// External Debug Interface
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// External Debug Interface
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
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);
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);
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| Line 77... |
Line 77... |
//
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//
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// RISC Internal Interface
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// RISC Internal Interface
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//
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//
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input clk; // Clock
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input clk; // Clock
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input rst; // Reset
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input rst; // Reset
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input [`LSUOP_WIDTH-1:0] dclsu_lsuop; // LSU status
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input [`FETCHOP_WIDTH-1:0] icfetch_op; // IFETCH unit status
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input ex_freeze; // EX stage freeze
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input [`BRANCHOP_WIDTH-1:0] branch_op; // Branch op
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output du_stall; // Debug Unit Stall
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output du_stall; // Debug Unit Stall
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output [aw-1:0] du_addr; // Debug Unit Address
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output [aw-1:0] du_addr; // Debug Unit Address
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input [dw-1:0] du_dat_i; // Debug Unit Data In
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input [dw-1:0] du_dat_i; // Debug Unit Data In
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output [dw-1:0] du_dat_o; // Debug Unit Data Out
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output [dw-1:0] du_dat_o; // Debug Unit Data Out
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output du_read; // Debug Unit Read Enable
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output du_read; // Debug Unit Read Enable
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| Line 89... |
Line 93... |
input spr_cs; // SPR Chip Select
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input spr_cs; // SPR Chip Select
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input spr_write; // SPR Read/Write
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input spr_write; // SPR Read/Write
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input [aw-1:0] spr_addr; // SPR Address
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input [aw-1:0] spr_addr; // SPR Address
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input [dw-1:0] spr_dat_i; // SPR Data Input
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input [dw-1:0] spr_dat_i; // SPR Data Input
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output [dw-1:0] spr_dat_o; // SPR Data Output
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output [dw-1:0] spr_dat_o; // SPR Data Output
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input [`LSUOP_WIDTH-1:0] dclsu_lsuop; // LSU status
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input [`FETCHOP_WIDTH-1:0] icfetch_op; // IFETCH unit status
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//
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//
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// External Debug Interface
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// External Debug Interface
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//
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//
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input dbg_stall_i; // External Stall Input
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input dbg_stall_i; // External Stall Input
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| Line 127... |
Line 129... |
assign du_write = (dbg_op_i == `DU_OP_WRITESPR);
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assign du_write = (dbg_op_i == `DU_OP_WRITESPR);
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`ifdef DU_IMPLEMENTED
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`ifdef DU_IMPLEMENTED
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//
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//
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// Debug Mode Register 1 (only ST and BT implemented)
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//
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`ifdef DU_DMR1
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reg [23:22] dmr1; // DMR1 implemented (ST & BT)
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`else
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wire [23:22] dmr1; // DMR1 not implemented
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`endif
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//
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// Debug Mode Register 2 (not implemented)
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//
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`ifdef DU_DMR2
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wire [31:0] dmr2; // DMR not implemented
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`endif
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//
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// Debug Stop Register
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// Debug Stop Register
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//
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//
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`ifdef DU_DSR
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`ifdef DU_DSR
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reg [13:0] dsr; // DSR implemented
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reg [13:0] dsr; // DSR implemented
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`else
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`else
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| Line 140... |
Line 158... |
//
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//
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// Debug Reason Register
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// Debug Reason Register
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//
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//
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`ifdef DU_DRR
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`ifdef DU_DRR
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reg [13:0] drr; // DRR implemented
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reg [13:0] drr; // DRR implemented
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wire [13:0] except_unmasked;
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reg [13:0] except_unmasked;
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`else
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`else
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wire [13:0] drr; // DRR not implemented
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wire [13:0] drr; // DRR not implemented
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`endif
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`endif
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//
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//
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// Internal wires
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// Internal wires
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//
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//
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wire [13:0] except_masked;
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wire [13:0] except_masked;
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wire dmr1_sel; // DMR1 select
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wire dsr_sel; // DSR select
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wire dsr_sel; // DSR select
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wire drr_sel; // DSR select
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wire drr_sel; // DRR select
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reg dbg_bp_r;
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`ifdef DU_READREGS
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`ifdef DU_READREGS
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reg [31:0] spr_dat_o;
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reg [31:0] spr_dat_o;
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`endif
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`endif
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//
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//
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// DU registers address decoder
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// DU registers address decoder
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//
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//
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`ifdef DU_DMR1
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assign dmr1_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DMR1));
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`endif
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`ifdef DU_DSR
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`ifdef DU_DSR
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assign dsr_sel = (spr_cs &&
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assign dsr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DSR));
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(spr_addr[`SPROFS_BITS] == `DU_OFS_DSR)) ? 1'b1 : 1'b0;
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`endif
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`endif
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`ifdef DU_DRR
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`ifdef DU_DRR
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assign drr_sel = (spr_cs &&
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assign drr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DRR));
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(spr_addr[`SPROFS_BITS] == `DU_OFS_DRR)) ? 1'b1 : 1'b0;
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`endif
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`endif
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//
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//
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// Decode started exception
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// Decode started exception
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//
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//
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Line 216... |
// Get only 'stop' exceptions
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// Get only 'stop' exceptions
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//
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//
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assign except_masked = dsr & except_unmasked;
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assign except_masked = dsr & except_unmasked;
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//
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//
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// Assert dbg_bp_o if one of 'stop' exceptions gets activated
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// dbg_bp_o is registered
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//
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//
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assign dbg_bp_o = |except_masked;
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assign dbg_bp_o = dbg_bp_r;
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//
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// Breakpoint activation register
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//
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always @(posedge clk or posedge rst)
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if (rst)
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// SIMON
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// dbg_bp_r <= #1 1'b1;
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dbg_bp_r <= #1 1'b0;
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else
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dbg_bp_r <= |except_masked
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`ifdef DU_DMR1_ST
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| ~ex_freeze & dmr1[`DU_DMR1_ST]
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`endif
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`ifdef DU_DMR1_BT
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| ~ex_freeze & (branch_op != `BRANCHOP_NOP) & dmr1[`DU_DMR1_BT]
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`endif
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;
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//
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// Write to DMR1
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//
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`ifdef DU_DMR1
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always @(posedge clk or posedge rst)
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if (rst)
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dmr1 <= 2'b00;
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else if (dmr1_sel && spr_write)
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dmr1 <= #1 spr_dat_i[23:22];
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`else
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assign dmr1 = 2'b00;
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`endif
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//
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// DMR2 bits tied to zero
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//
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`ifdef DU_DMR2
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assign dmr2 = 32'h0000_0000;
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`endif
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//
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//
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// Write to DSR
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// Write to DSR
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//
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//
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`ifdef DU_DSR
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`ifdef DU_DSR
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Line 280... |
always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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drr <= 14'b0;
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drr <= 14'b0;
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else if (drr_sel && spr_write)
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else if (drr_sel && spr_write)
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drr <= #1 spr_dat_i[13:0];
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drr <= #1 spr_dat_i[13:0];
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else (dbg_bp_o)
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else
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drr <= #1 drr | except_masked;
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drr <= #1 drr | except_masked;
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`else
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`else
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assign drr = 14'b0;
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assign drr = 14'b0;
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`endif
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`endif
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Line 292... |
// Read DU registers
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// Read DU registers
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//
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//
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`ifdef DU_READREGS
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`ifdef DU_READREGS
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always @(spr_addr or dsr or drr)
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always @(spr_addr or dsr or drr)
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case (spr_addr[`SPROFS_BITS])
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case (spr_addr[`SPROFS_BITS])
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`ifdef DU_DMR1
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`DU_OFS_DMR1:
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spr_dat_o = {8'b0, dmr1, 22'b0};
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`endif
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`ifdef DU_DMR2
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`DU_OFS_DMR2:
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spr_dat_o = dmr2;
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`endif
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`ifdef DU_DSR
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`ifdef DU_DSR
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`DU_OFS_DSR:
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`DU_OFS_DSR:
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spr_dat_o = {18'b0, dsr};
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spr_dat_o = {18'b0, dsr};
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`endif
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`endif
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`ifdef DU_DRR
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`ifdef DU_DRR
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