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Line 69... |
module frz_logic(
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module frz_logic(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// Internal i/f
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// Internal i/f
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multicycle, except_flushpipe, lsu_stall, if_stall, dclsu_unstall, branch_stall, force_dslot_fetch,
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multicycle, except_flushpipe, lsu_stall, if_stall,
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dclsu_unstall, branch_stall, du_stall, mac_stall,
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force_dslot_fetch,
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if_freeze, id_freeze, ex_freeze, wb_freeze
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if_freeze, id_freeze, ex_freeze, wb_freeze
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);
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);
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//
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//
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// I/O
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// I/O
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Line 87... |
input lsu_stall;
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input lsu_stall;
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input if_stall;
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input if_stall;
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input dclsu_unstall;
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input dclsu_unstall;
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input branch_stall;
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input branch_stall;
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input force_dslot_fetch;
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input force_dslot_fetch;
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input du_stall;
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input mac_stall;
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output if_freeze;
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output if_freeze;
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output id_freeze;
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output id_freeze;
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output ex_freeze;
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output ex_freeze;
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output wb_freeze;
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output wb_freeze;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg multicycle_freeze;
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reg multicycle_freeze;
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reg [1:0] state;
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reg [2:0] state2;
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reg [2:0] state2;
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reg [2:0] multicycle_cnt;
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reg [2:0] multicycle_cnt;
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reg done_once;
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reg done_once;
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//
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//
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// Pipeline freeze
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// Pipeline freeze
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//
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//
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assign if_freeze = id_freeze;
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// Rules how to create freeze signals:
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assign id_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~except_flushpipe;
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// 1. Not overwriting pipeline stages:
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assign ex_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze) & ~except_flushpipe;
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// Frreze signals at the beginning of pipeline (such as if_freeze) can be asserted more
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assign wb_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze) & ~except_flushpipe;
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// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
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// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
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//
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// 2. Inserting NOPs in the middle of pipeline only if supported:
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// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
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// This way NOP is asserted from stage ID into EX stage.
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//
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//
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// Freeze FSM1
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assign if_freeze = id_freeze;
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//
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assign id_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~except_flushpipe | du_stall;
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always @(posedge clk or posedge rst) begin
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assign ex_freeze = wb_freeze;
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if (rst) begin
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assign wb_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze) & ~except_flushpipe | du_stall | mac_stall;
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state <= #1 `NO_FREEZE;
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end
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else
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case (state) // synopsys full_case parallel_case
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`NO_FREEZE :
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if (lsu_stall) begin
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state <= #1 `FREEZE_BYDC;
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end
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`FREEZE_BYDC :
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if (!lsu_stall) begin
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state <= #1 `NO_FREEZE;
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end
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endcase
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end
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//
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//
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// Freeze FSM2
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// Freeze FSM2
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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Line 162... |
else begin
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else begin
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state2 <= #1 `NO_FREEZE;
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state2 <= #1 `NO_FREEZE;
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multicycle_freeze <= #1 1'b0;
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multicycle_freeze <= #1 1'b0;
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end
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end
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`WAIT_LSU_TO_FINISH:
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`WAIT_LSU_TO_FINISH:
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if (!lsu_stall && !multicycle) begin
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if (!lsu_stall && !(|multicycle)) begin
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state2 <= #1 `NO_FREEZE;
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state2 <= #1 `NO_FREEZE;
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end
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end
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else if (!lsu_stall && multicycle) begin
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else if (!lsu_stall & (|multicycle)) begin
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state2 <= #1 `FREEZE_BYMULTICYCLE;
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state2 <= #1 `FREEZE_BYMULTICYCLE;
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multicycle_freeze <= #1 1'b1;
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multicycle_freeze <= #1 1'b1;
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multicycle_cnt <= #1 multicycle - 'd1;
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multicycle_cnt <= #1 multicycle - 'd1;
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end
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end
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endcase
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endcase
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