URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [generic_dpram_32x32.v] - Diff between revs 218 and 220

Rev 218	Rev 220
Line 59...	Line 59...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.7 2001/10/21 17:57:16 lampret`
	`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
	`//`
`// Revision 1.6 2001/10/14 13:12:09 lampret`	`// Revision 1.6 2001/10/14 13:12:09 lampret`
`// MP3 version.`	`// MP3 version.`
`//`	`//`
`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`	`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
`// no message`	`// no message`
Line 120...	Line 123...
`// Artisan Synchronous Double-Port RAM (ra2sh)`	`// Artisan Synchronous Double-Port RAM (ra2sh)`
`//`	`//`
`ifdef UNUSED	`ifdef UNUSED
`art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(`	`art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(`
`else	`else
`art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(`	`art_hsdp_32x32 artisan_sdp(`
`endif	`endif
`.qa(do_a),`	`.qa(do_a),`
`.clka(clk_a),`	`.clka(clk_a),`
`.cena(~ce_a),`	`.cena(~ce_a),`
`.wena(1'b1),`	`.wena(1'b1),`