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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2001/10/22 19:39:56 lampret
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// Fixed parameters in generic sprams.
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//
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// Revision 1.7 2001/10/21 17:57:16 lampret
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// Revision 1.7 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.6 2001/10/14 13:12:09 lampret
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// Revision 1.6 2001/10/14 13:12:09 lampret
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// MP3 version.
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// MP3 version.
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Line 192... |
Line 195... |
.CLKB(clk_b)
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.CLKB(clk_b)
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);
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);
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`else
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`else
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`ifdef VIRTUALSILICON_STP
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//
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// Instantiation of ASIC memory:
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//
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// Virtual Silicon Two-port R/W SRAM
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//
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`ifdef UNUSED
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vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(
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`else
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vs_hdtp_32x32 vs_ssp(
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`endif
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.RCK(clk_a),
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.REN(~ce_a),
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.OEN(~oe_a),
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.RADR(addr_a),
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.DI(di_b),
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.WCK(clk_b),
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.WEN(~ce_b),
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.WADR(addr_b),
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.DOUT(do_a)
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);
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`else
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`ifdef XILINX_RAM32X1D
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`ifdef XILINX_RAM32X1D
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//
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//
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// Instantiation of FPGA memory:
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// Instantiation of FPGA memory:
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//
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//
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