URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [generic_dpram_32x32.v] - Diff between revs 220 and 265

Rev 220	Rev 265
Line 59...	Line 59...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.8 2001/10/22 19:39:56 lampret`
	`// Fixed parameters in generic sprams.`
	`//`
`// Revision 1.7 2001/10/21 17:57:16 lampret`	`// Revision 1.7 2001/10/21 17:57:16 lampret`
`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`	`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
`//`	`//`
`// Revision 1.6 2001/10/14 13:12:09 lampret`	`// Revision 1.6 2001/10/14 13:12:09 lampret`
`// MP3 version.`	`// MP3 version.`
Line 192...	Line 195...
`.CLKB(clk_b)`	`.CLKB(clk_b)`
`);`	`);`

`else	`else

	`ifdef VIRTUALSILICON_STP

	`//`
	`// Instantiation of ASIC memory:`
	`//`
	`// Virtual Silicon Two-port R/W SRAM`
	`//`
	`ifdef UNUSED
	`vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
	`else
	`vs_hdtp_32x32 vs_ssp(`
	`endif
	`.RCK(clk_a),`
	`.REN(~ce_a),`
	`.OEN(~oe_a),`
	`.RADR(addr_a),`
	`.DI(di_b),`
	`.WCK(clk_b),`
	`.WEN(~ce_b),`
	`.WADR(addr_b),`
	`.DOUT(do_a)`
	`);`

	`else

`ifdef XILINX_RAM32X1D	`ifdef XILINX_RAM32X1D

`//`	`//`
`// Instantiation of FPGA memory:`	`// Instantiation of FPGA memory:`
`//`	`//`