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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [generic_spram_2048x32.v] - Diff between revs 168 and 203

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Rev 168	Rev 203
Line 60...	Line 60...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2001/08/09 13:39:33 lampret`
	`// Major clean-up.`
	`//`
`// Revision 1.2 2001/07/30 05:38:02 lampret`	`// Revision 1.2 2001/07/30 05:38:02 lampret`
`// Adding empty directories required by HDL coding guidelines`	`// Adding empty directories required by HDL coding guidelines`
`//`	`//`
`//`	`//`

	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
	`// synopsys translate_on`
	`include "defines.v"

`module generic_spram_2048x32(`	`module generic_spram_2048x32(`
`// Generic synchronous single-port RAM interface`	`// Generic synchronous single-port RAM interface`
`clk, rst, ce, we, oe, addr, di, do`	`clk, rst, ce, we, oe, addr, di, do`
`);`	`);`
Line 102...	Line 108...
`//`	`//`
`// Instantiation of ASIC memory:`	`// Instantiation of ASIC memory:`
`//`	`//`
`// Artisan Synchronous Single-Port RAM (ra1sh)`	`// Artisan Synchronous Single-Port RAM (ra1sh)`
`//`	`//`
`art_hdsp_2048x32 #(dw, 2<<aw, aw) artisan_ssp(`	`art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp(`
`.clk(clk),`	`.clk(clk),`
`.cen(~ce),`	`.cen(~ce),`
`.wen(~we),`	`.wen(~we),`
`.a(addr),`	`.a(addr),`
`.d(di),`	`.d(di),`
Line 161...	Line 167...
`//`	`//`
`// Instantiation of ASIC memory:`	`// Instantiation of ASIC memory:`
`//`	`//`
`// Virtual Silicon Single-Port Synchronous SRAM`	`// Virtual Silicon Single-Port Synchronous SRAM`
`//`	`//`
`virtualsilicon_ssp #(2<<aw, aw-1, dw-1) virtualsilicon_ssp(`	`virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(`
`.CK(clk),`	`.CK(clk),`
`.ADR(addr),`	`.ADR(addr),`
`.DI(di),`	`.DI(di),`
`.WEN(~we),`	`.WEN(~we),`
`.CEN(~ce),`	`.CEN(~ce),`
Line 398...	Line 404...
`//`	`//`

`//`	`//`
`// Generic RAM's registers and wires`	`// Generic RAM's registers and wires`
`//`	`//`
`reg [dw-1:0] mem [(2<<aw)-1:0]; // RAM content`	`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
`reg [dw-1:0] do_reg; // RAM data output register`	`reg [dw-1:0] do_reg; // RAM data output register`

`//`	`//`
`// Data output drivers`	`// Data output drivers`
`//`	`//`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [generic_spram_2048x32.v] - Diff between revs 168 and 203