URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [generic_spram_2048x32.v] - Diff between revs 218 and 265

Rev 218	Rev 265
Line 60...	Line 60...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.7 2001/10/21 17:57:16 lampret`
	`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
	`//`
`// Revision 1.6 2001/10/14 13:12:09 lampret`	`// Revision 1.6 2001/10/14 13:12:09 lampret`
`// MP3 version.`	`// MP3 version.`
`//`	`//`
`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`	`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
`// no message`	`// no message`
Line 177...	Line 180...
`//`	`//`
`// Instantiation of ASIC memory:`	`// Instantiation of ASIC memory:`
`//`	`//`
`// Virtual Silicon Single-Port Synchronous SRAM`	`// Virtual Silicon Single-Port Synchronous SRAM`
`//`	`//`
`virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(`	`ifdef UNUSED
	`vs_hdsp_2048x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
	`else
	`vs_hdsp_2048x32 vs_ssp(`
	`endif
`.CK(clk),`	`.CK(clk),`
`.ADR(addr),`	`.ADR(addr),`
`.DI(di),`	`.DI(di),`
`.WEN(~we),`	`.WEN(~we),`
`.CEN(~ce),`	`.CEN(~ce),`