URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [generic_spram_64x14.v] - Diff between revs 215 and 218

Rev 215	Rev 218
Line 60...	Line 60...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.5 2001/10/14 13:12:09 lampret`
	`// MP3 version.`
	`//`
`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`	`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
`// no message`	`// no message`
`//`	`//`
`// Revision 1.1 2001/08/09 13:39:33 lampret`	`// Revision 1.1 2001/08/09 13:39:33 lampret`
`// Major clean-up.`	`// Major clean-up.`
Line 111...	Line 114...
`//`	`//`
`// Instantiation of ASIC memory:`	`// Instantiation of ASIC memory:`
`//`	`//`
`// Artisan Synchronous Single-Port RAM (ra1sh)`	`// Artisan Synchronous Single-Port RAM (ra1sh)`
`//`	`//`
	`ifdef UNUSED
`art_hssp_64x14 #(dw, 1<<aw, aw) artisan_ssp(`	`art_hssp_64x14 #(dw, 1<<aw, aw) artisan_ssp(`
	`else
	`art_hssp_64x14 artisan_ssp(`
	`endif
`.clk(clk),`	`.clk(clk),`
`.cen(~ce),`	`.cen(~ce),`
`.wen(~we),`	`.wen(~we),`
`.a(addr),`	`.a(addr),`
`.d(di),`	`.d(di),`