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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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`include "defines.v"
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`include "defines.v"
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module ic_ram(
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module ic_ram(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// Internal i/f
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// Internal i/f
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addr, we, datain, dataout
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addr, en, we, datain, dataout
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);
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);
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parameter dw = `OPERAND_WIDTH;
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parameter dw = `OPERAND_WIDTH;
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parameter aw = `ICINDX;
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parameter aw = `ICINDX;
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// I/O
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// I/O
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input [aw-1:0] addr;
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input [aw-1:0] addr;
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input en;
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input [3:0] we;
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input [3:0] we;
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input [dw-1:0] datain;
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input [dw-1:0] datain;
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output [dw-1:0] dataout;
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output [dw-1:0] dataout;
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`ifdef OR1200_NO_IC
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//
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// Insn cache not implemented
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//
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assign dataout = {dw{1'b0}};
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`else
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//
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//
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// Instantiation of 2048x32 RAM block
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// Instantiation of 2048x32 RAM block
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//
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//
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generic_spram_2048x32 ic_ram0(
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generic_spram_2048x32 ic_ram0(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.ce(1'b1),
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.ce(en),
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.we(we[0]),
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.we(we[0]),
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.oe(1'b1),
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.oe(1'b1),
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.addr(addr),
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.addr(addr),
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.di(datain),
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.di(datain),
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.do(dataout)
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.do(dataout)
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);
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);
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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