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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [ic_tag.v] - Diff between revs 203 and 205

Rev 203	Rev 205
Line 60...	Line 60...
`module ic_tag(`	`module ic_tag(`
`// Clock and reset`	`// Clock and reset`
`clk, rst,`	`clk, rst,`

`// Internal i/f`	`// Internal i/f`
`addr, en, we, datain, dataout`	`addr, en, we, datain, tag_v, tag`
`);`	`);`

`parameter dw = 19;`	`parameter dw = 20;`
`parameter aw = 9;`	`parameter aw = 9;`

`//`	`//`
`// I/O`	`// I/O`
`//`	`//`
Line 83...	Line 83...
`//`	`//`
`input [aw-1:0] addr;`	`input [aw-1:0] addr;`
`input en;`	`input en;`
`input we;`	`input we;`
`input [dw-1:0] datain;`	`input [dw-1:0] datain;`
`output [dw-1:0] dataout;`	`output tag_v;`
	`output [dw-2:0] tag;`

`ifdef OR1200_NO_IC	`ifdef OR1200_NO_IC

`//`	`//`
`// Insn cache not implemented`	`// Insn cache not implemented`
`//`	`//`
`assign dataout = {dw{1'b0}};`	`assign tag = {dw{1'b0}};`
	`assign tag_v = 1'b0;`
`else	`else

`//`	`//`
`// Instantiation of TAG RAM block`	`// Instantiation of TAG RAM block`
`//`	`//`
`generic_spram_512x19 ic_tag0(`	`generic_spram_512x20 ic_tag0(`
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we),`	`.we(we),`
`.oe(1'b1),`	`.oe(1'b1),`
`.addr(addr),`	`.addr(addr),`
`.di(datain),`	`.di(datain),`
`.do(dataout)`	`.do({tag, tag_v})`
`);`	`);`

`endif	`endif

`endmodule`	`endmodule`