| Line 58... |
Line 58... |
module id(
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module id(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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|
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// Internal i/f
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// Internal i/f
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pipeline_freeze, except_flushpipe, if_insn, branch_op,
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id_freeze, ex_freeze, wb_freeze, except_flushpipe, if_insn, branch_op,
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rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,
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rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,
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wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
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wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
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multicycle, spr_addrimm, wbforw_valid, sig_syscall,
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multicycle, spr_addrimm, wbforw_valid, sig_syscall,
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force_dslot_fetch
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force_dslot_fetch
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);
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);
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| Line 70... |
Line 70... |
//
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//
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// I/O
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// I/O
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input pipeline_freeze;
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input id_freeze;
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input ex_freeze;
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input wb_freeze;
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input except_flushpipe;
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input except_flushpipe;
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input [31:0] if_insn;
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input [31:0] if_insn;
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output [`BRANCHOP_WIDTH-1:0] branch_op;
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output [`BRANCHOP_WIDTH-1:0] branch_op;
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output [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
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output [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
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output [`REGFILE_ADDR_WIDTH-1:0] rf_addra;
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output [`REGFILE_ADDR_WIDTH-1:0] rf_addra;
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| Line 176... |
Line 178... |
// Decode of spr_addrimm
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// Decode of spr_addrimm
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//
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//
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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if (rst_or_except_flushpipe)
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if (rst_or_except_flushpipe)
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spr_addrimm <= #1 16'h0000;
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spr_addrimm <= #1 16'h0000;
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else if (!pipeline_freeze) begin
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else if (!ex_freeze & id_freeze)
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spr_addrimm <= #1 16'h0000;
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else if (!ex_freeze) begin
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case (id_insn[31:26]) // synopsys full_case parallel_case
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case (id_insn[31:26]) // synopsys full_case parallel_case
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// l.mtspr
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// l.mtspr
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`OR32_MTSPR:
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`OR32_MTSPR:
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spr_addrimm <= #1 id_insn[15:0];
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spr_addrimm <= #1 id_insn[15:0];
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// l.mfspr
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// l.mfspr
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| Line 297... |
Line 301... |
// Register file write address
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// Register file write address
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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rf_addrw <= #1 5'd0;
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rf_addrw <= #1 5'd0;
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else if (!pipeline_freeze)
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else if (!ex_freeze & id_freeze)
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rf_addrw <= #1 5'd00;
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else if (!ex_freeze)
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case (pre_branch_op) // synopsys parallel_case full_case
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case (pre_branch_op) // synopsys parallel_case full_case
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`BRANCHOP_JR, `BRANCHOP_BAL:
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`BRANCHOP_JR, `BRANCHOP_BAL:
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rf_addrw <= #1 5'd09; // link register r9
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rf_addrw <= #1 5'd09; // link register r9
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default:
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default:
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rf_addrw <= #1 id_insn[25:21];
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rf_addrw <= #1 id_insn[25:21];
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| Line 312... |
Line 318... |
// rf_addrw in wb stage (used in forwarding logic)
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// rf_addrw in wb stage (used in forwarding logic)
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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wb_rfaddrw <= #1 5'd0;
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wb_rfaddrw <= #1 5'd0;
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else if (!pipeline_freeze)
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else if (!wb_freeze)
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wb_rfaddrw <= #1 rf_addrw;
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wb_rfaddrw <= #1 rf_addrw;
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end
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end
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//
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//
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// Instruction latch in id_insn
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// Instruction latch in id_insn
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| Line 324... |
Line 330... |
always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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id_insn[31:26] <= #1 `OR32_NOP;
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id_insn[31:26] <= #1 `OR32_NOP;
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id_insn[25:0] <= #1 26'd0;
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id_insn[25:0] <= #1 26'd0;
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end
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end
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else if (!pipeline_freeze) begin
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else if (!id_freeze) begin
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id_insn <= #1 if_insn;
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id_insn <= #1 if_insn;
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: id_insn <= %h", $time, if_insn);
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$display("%t: id_insn <= %h", $time, if_insn);
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// synopsys translate_on
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// synopsys translate_on
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| Line 342... |
Line 348... |
always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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ex_insn[31:26] <= #1 `OR32_NOP;
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ex_insn[31:26] <= #1 `OR32_NOP;
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ex_insn[25:0] <= #1 26'd0;
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ex_insn[25:0] <= #1 26'd0;
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end
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end
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else if (!pipeline_freeze) begin
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else if (!ex_freeze & id_freeze)
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ex_insn <= #1 {`OR32_NOP, 26'h000_4444};
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else if (!ex_freeze) begin
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ex_insn <= #1 id_insn;
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ex_insn <= #1 id_insn;
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: ex_insn <= %h", $time, id_insn);
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$display("%t: ex_insn <= %h", $time, id_insn);
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// synopsys translate_on
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// synopsys translate_on
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| Line 360... |
Line 368... |
always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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wb_insn[31:26] <= #1 `OR32_NOP;
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wb_insn[31:26] <= #1 `OR32_NOP;
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wb_insn[25:0] <= #1 26'd0;
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wb_insn[25:0] <= #1 26'd0;
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end
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end
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else if (!pipeline_freeze) begin
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else if (!wb_freeze) begin
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wb_insn <= #1 ex_insn;
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wb_insn <= #1 ex_insn;
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end
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end
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end
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end
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//
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//
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// Decode of sel_imm
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// Decode of sel_imm
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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sel_imm <= #1 1'b0;
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sel_imm <= #1 1'b0;
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else if (!pipeline_freeze) begin
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else if (!id_freeze) begin
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case (if_insn[31:26]) // synopsys full_case parallel_case
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case (if_insn[31:26]) // synopsys full_case parallel_case
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// j.jalr
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// j.jalr
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`OR32_JALR:
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`OR32_JALR:
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sel_imm <= #1 `off;
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sel_imm <= #1 `off;
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| Line 439... |
Line 447... |
// Decode of alu_op
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// Decode of alu_op
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//
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//
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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if (rst_or_except_flushpipe)
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if (rst_or_except_flushpipe)
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alu_op <= #1 `ALUOP_NOP;
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alu_op <= #1 `ALUOP_NOP;
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else if (!pipeline_freeze) begin
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else if (!ex_freeze & id_freeze)
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alu_op <= #1 `ALUOP_NOP;
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else if (!ex_freeze) begin
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case (id_insn[31:26]) // synopsys full_case parallel_case
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case (id_insn[31:26]) // synopsys full_case parallel_case
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// l.j
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// l.j
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`OR32_J:
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`OR32_J:
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alu_op <= #1 `ALUOP_IMM;
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alu_op <= #1 `ALUOP_IMM;
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| Line 587... |
Line 597... |
// Decode of shrot_op
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// Decode of shrot_op
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//
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//
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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if (rst_or_except_flushpipe)
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if (rst_or_except_flushpipe)
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shrot_op <= #1 `SHROTOP_NOP;
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shrot_op <= #1 `SHROTOP_NOP;
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else if (!pipeline_freeze) begin
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else if (!ex_freeze & id_freeze)
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shrot_op <= #1 `SHROTOP_NOP;
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else if (!ex_freeze) begin
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shrot_op <= #1 id_insn[`SHROTOP_POS];
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shrot_op <= #1 id_insn[`SHROTOP_POS];
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end
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end
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end
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end
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//
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//
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// Decode of rfwb_op
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// Decode of rfwb_op
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//
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//
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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if (rst_or_except_flushpipe)
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if (rst_or_except_flushpipe)
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rfwb_op <= #1 `RFWBOP_NOP;
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rfwb_op <= #1 `RFWBOP_NOP;
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else if (!pipeline_freeze) begin
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else if (!ex_freeze & id_freeze)
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rfwb_op <= #1 `RFWBOP_NOP;
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else if (!ex_freeze) begin
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case (id_insn[31:26]) // synopsys full_case parallel_case
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case (id_insn[31:26]) // synopsys full_case parallel_case
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|
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// j.jal
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// j.jal
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`OR32_JAL:
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`OR32_JAL:
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rfwb_op <= #1 `RFWBOP_LR;
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rfwb_op <= #1 `RFWBOP_LR;
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| Line 688... |
Line 702... |
// Decode of pre_branch_op
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// Decode of pre_branch_op
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//
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//
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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if (rst_or_except_flushpipe)
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if (rst_or_except_flushpipe)
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pre_branch_op <= #1 `BRANCHOP_NOP;
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pre_branch_op <= #1 `BRANCHOP_NOP;
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else if (!pipeline_freeze) begin
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else if (!id_freeze) begin
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case (if_insn[31:26]) // synopsys full_case parallel_case
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case (if_insn[31:26]) // synopsys full_case parallel_case
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|
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// l.j
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// l.j
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`OR32_J:
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`OR32_J:
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pre_branch_op <= #1 `BRANCHOP_BAL;
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pre_branch_op <= #1 `BRANCHOP_BAL;
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| Line 733... |
Line 747... |
// Generation of branch_op
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// Generation of branch_op
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//
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//
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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if (rst_or_except_flushpipe)
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if (rst_or_except_flushpipe)
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branch_op <= #1 `BRANCHOP_NOP;
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branch_op <= #1 `BRANCHOP_NOP;
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else if (!pipeline_freeze) begin
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else if (!ex_freeze & id_freeze)
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branch_op <= #1 `BRANCHOP_NOP;
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else if (!ex_freeze) begin
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branch_op <= #1 pre_branch_op;
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branch_op <= #1 pre_branch_op;
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end
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end
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end
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end
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|
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//
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//
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// Decode of lsu_op
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// Decode of lsu_op
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//
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//
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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if (rst_or_except_flushpipe)
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if (rst_or_except_flushpipe)
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lsu_op <= #1 `LSUOP_NOP;
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lsu_op <= #1 `LSUOP_NOP;
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else if (!pipeline_freeze) begin
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else if (!ex_freeze & id_freeze)
|
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lsu_op <= #1 `LSUOP_NOP;
|
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else if (!ex_freeze) begin
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case (id_insn[31:26]) // synopsys full_case parallel_case
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case (id_insn[31:26]) // synopsys full_case parallel_case
|
|
|
// l.lwz
|
// l.lwz
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`OR32_LWZ:
|
`OR32_LWZ:
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lsu_op <= #1 `LSUOP_LWZ;
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lsu_op <= #1 `LSUOP_LWZ;
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| Line 793... |
Line 811... |
// Decode of comp_op
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// Decode of comp_op
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//
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//
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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always @(posedge clk or posedge rst_or_except_flushpipe) begin
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if (rst_or_except_flushpipe)
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if (rst_or_except_flushpipe)
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comp_op <= #1 4'd0;
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comp_op <= #1 4'd0;
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else if (!pipeline_freeze) begin
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else if (!ex_freeze & id_freeze)
|
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comp_op <= #1 4'd0;
|
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else if (!ex_freeze) begin
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comp_op <= #1 id_insn[24:21];
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comp_op <= #1 id_insn[24:21];
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end
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end
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end
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end
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|
|
//
|
//
|
// Decode of l.sys
|
// Decode of l.sys
|
//
|
//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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sig_syscall <= #1 1'b0;
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sig_syscall <= #1 1'b0;
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else if (!pipeline_freeze) begin
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else if (!wb_freeze) begin
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`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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if (wb_insn[31:24] == {`OR32_XSYNC, 2'b00})
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if (wb_insn[31:24] == {`OR32_XSYNC, 2'b00})
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$display("Generating sig_syscall");
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$display("Generating sig_syscall");
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// synopsys translate_on
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// synopsys translate_on
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