| Line 61... |
Line 61... |
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// Internal i/f
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// Internal i/f
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id_freeze, ex_freeze, wb_freeze, except_flushpipe, if_insn, branch_op,
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id_freeze, ex_freeze, wb_freeze, except_flushpipe, if_insn, branch_op,
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rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,
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rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,
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wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
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wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
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multicycle, spr_addrimm, wbforw_valid, sig_syscall,
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multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap,
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force_dslot_fetch, id_macrc_op, ex_macrc_op
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force_dslot_fetch, id_macrc_op, ex_macrc_op
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);
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);
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//
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//
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// I/O
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// I/O
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| Line 94... |
Line 94... |
output [`COMPOP_WIDTH-1:0] comp_op;
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output [`COMPOP_WIDTH-1:0] comp_op;
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output [`MULTICYCLE_WIDTH-1:0] multicycle;
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output [`MULTICYCLE_WIDTH-1:0] multicycle;
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output [15:0] spr_addrimm;
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output [15:0] spr_addrimm;
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input wbforw_valid;
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input wbforw_valid;
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output sig_syscall;
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output sig_syscall;
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output sig_trap;
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output force_dslot_fetch;
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output force_dslot_fetch;
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output id_macrc_op;
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output id_macrc_op;
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output ex_macrc_op;
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output ex_macrc_op;
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//
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//
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| Line 121... |
Line 122... |
reg [`COMPOP_WIDTH-1:0] comp_op;
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reg [`COMPOP_WIDTH-1:0] comp_op;
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reg [`MULTICYCLE_WIDTH-1:0] multicycle;
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reg [`MULTICYCLE_WIDTH-1:0] multicycle;
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reg imm_signextend;
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reg imm_signextend;
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reg [15:0] spr_addrimm;
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reg [15:0] spr_addrimm;
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reg sig_syscall;
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reg sig_syscall;
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reg sig_trap;
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wire rst_or_except_flushpipe;
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wire rst_or_except_flushpipe;
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reg ex_macrc_op;
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reg ex_macrc_op;
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//
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//
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// Register file read addresses
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// Register file read addresses
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| Line 844... |
Line 846... |
// Decode of l.sys
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// Decode of l.sys
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//
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//
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always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
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if (rst)
|
if (rst)
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sig_syscall <= #1 1'b0;
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sig_syscall <= #1 1'b0;
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else if (!wb_freeze) begin
|
else if (!ex_freeze & id_freeze)
|
|
sig_syscall <= #1 1'b0;
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else if (!ex_freeze) begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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if (wb_insn[31:24] == {`OR32_XSYNC, 2'b00})
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if (id_insn[31:23] == {`OR32_XSYNC, 3'b000})
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$display("Generating sig_syscall");
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$display("Generating sig_syscall");
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// synopsys translate_on
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// synopsys translate_on
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`endif
|
`endif
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// sig_syscall <= #1 (wb_insn[31:24] == {`OR32_XSYNC, 2'b00});
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// sig_syscall <= #1 (id_insn[31:23] == {`OR32_XSYNC, 3'b000});
|
|
end
|
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end
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|
|
//
|
|
// Decode of l.trap
|
|
//
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst)
|
|
sig_trap <= #1 1'b0;
|
|
else if (!ex_freeze & id_freeze)
|
|
sig_trap <= #1 1'b0;
|
|
else if (!ex_freeze) begin
|
|
`ifdef OR1200_VERBOSE
|
|
// synopsys translate_off
|
|
if (id_insn[31:23] == {`OR32_XSYNC, 3'b010})
|
|
$display("Generating sig_trap");
|
|
// synopsys translate_on
|
|
`endif
|
|
sig_trap <= #1 (id_insn[31:23] == {`OR32_XSYNC, 3'b010});
|
end
|
end
|
end
|
end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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