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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [id.v] - Diff between revs 210 and 215

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Rev 210 Rev 215
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
 
// no message
 
//
// Revision 1.2  2001/08/13 03:36:20  lampret
// Revision 1.2  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
// Major clean-up.
Line 204... Line 207...
                spr_addrimm <= #1 16'h0000;
                spr_addrimm <= #1 16'h0000;
        else if (!ex_freeze & id_freeze)
        else if (!ex_freeze & id_freeze)
                spr_addrimm <= #1 16'h0000;
                spr_addrimm <= #1 16'h0000;
        else if (!ex_freeze) begin
        else if (!ex_freeze) begin
                case (id_insn[31:26])   // synopsys full_case parallel_case
                case (id_insn[31:26])   // synopsys full_case parallel_case
                        // l.mtspr
 
                        `OR32_MTSPR:
 
                                spr_addrimm <= #1 id_insn[15:0];
 
                        // l.mfspr
                        // l.mfspr
 
                        `OR32_MFSPR:
 
                                spr_addrimm <= #1 id_insn[15:0];
 
                        // l.mtspr
                        default:
                        default:
                                spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};
                                spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};
                endcase
                endcase
        end
        end
end
end
Line 855... Line 858...
// synopsys translate_off
// synopsys translate_off
                if (id_insn[31:23] == {`OR32_XSYNC, 3'b000})
                if (id_insn[31:23] == {`OR32_XSYNC, 3'b000})
                        $display("Generating sig_syscall");
                        $display("Generating sig_syscall");
// synopsys translate_on
// synopsys translate_on
`endif
`endif
//              sig_syscall <= #1 (id_insn[31:23] == {`OR32_XSYNC, 3'b000});
                sig_syscall <= #1 (id_insn[31:23] == {`OR32_XSYNC, 3'b000});
        end
        end
end
end
 
 
//
//
// Decode of l.trap
// Decode of l.trap

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