| Line 60... |
Line 60... |
|
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// External i/f to IC
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// External i/f to IC
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ic_insn, ic_addr, ic_stall, ic_fetchop, tp_insn, tp_wr_insn,
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ic_insn, ic_addr, ic_stall, ic_fetchop, tp_insn, tp_wr_insn,
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|
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// Internal i/f
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// Internal i/f
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pipeline_freeze, if_insn, if_pc, branch_op, except_type,
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if_freeze, if_insn, if_pc, branch_op, except_type,
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branch_addrofs, lr_restor, flag, taken, binsn_addr, except_start,
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branch_addrofs, lr_restor, flag, taken, binsn_addr, except_start,
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epcr, force_dslot_fetch, if_stall, branch_stall
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epcr, force_dslot_fetch, if_stall, branch_stall
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);
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);
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|
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//
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//
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| Line 88... |
Line 88... |
input tp_wr_insn;
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input tp_wr_insn;
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|
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//
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//
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// Internal i/f
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// Internal i/f
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//
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//
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input pipeline_freeze;
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input if_freeze;
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output [31:0] if_insn;
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output [31:0] if_insn;
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output [31:0] if_pc;
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output [31:0] if_pc;
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input [`BRANCHOP_WIDTH-1:0] branch_op;
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input [`BRANCHOP_WIDTH-1:0] branch_op;
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input [`EXCEPT_WIDTH-1:0] except_type;
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input [`EXCEPT_WIDTH-1:0] except_type;
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input [31:2] branch_addrofs;
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input [31:2] branch_addrofs;
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| Line 250... |
Line 250... |
// PC register
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// PC register
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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pcreg <= #1 30'd64;
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pcreg <= #1 30'd64;
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else if (!pipeline_freeze && !ic_stall) begin
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else if (!if_freeze && !ic_stall) begin
|
pcreg <= #1 ic_addr[31:2];
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pcreg <= #1 ic_addr[31:2];
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: pcreg incremented to %h", $time, {ic_addr[31:2], 2'b0});
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$display("%t: pcreg incremented to %h", $time, {ic_addr[31:2], 2'b0});
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// synopsys translate_on
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// synopsys translate_on
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| Line 267... |
Line 267... |
//
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//
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always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
|
if_saved <= #1 33'b0;
|
if_saved <= #1 33'b0;
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end
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end
|
else if (pipeline_freeze && !if_saved[32] && !ic_stall) begin // && !taken
|
else if (if_freeze && !if_saved[32] && !ic_stall) begin // && !taken
|
if_saved <= #1 {1'b1, ic_tp_insn};
|
if_saved <= #1 {1'b1, ic_tp_insn};
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: if_saved <= %h", $time, {1'b1, ic_tp_insn});
|
$display("%t: if_saved <= %h", $time, {1'b1, ic_tp_insn});
|
// synopsys translate_on
|
// synopsys translate_on
|
`endif
|
`endif
|
end
|
end
|
else if (!pipeline_freeze) begin
|
else if (!if_freeze) begin
|
if_saved[32] <= #1 1'b0;
|
if_saved[32] <= #1 1'b0;
|
if_saved[31:0] <= #1 32'h1500eeee;
|
if_saved[31:0] <= #1 32'h1500eeee;
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
// synopsys translate_off
|
// synopsys translate_off
|
$display("%t: if_saved[32] <= 0", $time);
|
$display("%t: if_saved[32] <= 0", $time);
|
| Line 292... |
Line 292... |
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
pc_saved <= #1 32'b0;
|
pc_saved <= #1 32'b0;
|
end
|
end
|
else if (pipeline_freeze && !if_saved[32] && !ic_stall) begin // && !taken
|
else if (if_freeze && !if_saved[32] && !ic_stall) begin // && !taken
|
pc_saved <= #1 ic_addr;
|
pc_saved <= #1 ic_addr;
|
end
|
end
|
else if (!pipeline_freeze) begin
|
else if (!if_freeze) begin
|
pc_saved <= #1 32'h00000000;
|
pc_saved <= #1 32'h00000000;
|
end
|
end
|
|
|
endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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